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HT95R35 Datasheet(PDF) 47 Page - Holtek Semiconductor Inc |
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HT95R35 Datasheet(HTML) 47 Page - Holtek Semiconductor Inc |
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47 / 73 page ![]() HT95R35 Rev. 1.00 47 October 7, 2009 Wake-up A reset, interrupt or port A wake-up can all wake up the device from the Sleep Mode or the Idle Mode. A reset can include a power-on reset, an external reset or a WDT time-out reset. By examining the device status flags, PDF and TO, the program can distinguish be- tween the different reset conditions. Refer to the Reset section for a more detailed description. A port A wake-up and an interrupt can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device using configuration options. When awakened by a Port A stimulus, the program will resume execution at the next instruction following the HALT instruction. Any valid interrupt during the Sleep Mode or Idle Mode may have one of two consequences. One is if the re- lated interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. The other is if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. It is necessary to mention that if an interrupt request flag is set to "1" before entering the Sleep mode or Idle mode, the Wake-up function of the related inter- rupt will be disabled. Once a Sleep mode or Idle mode Wake-up event oc- curs, it will take an SST delay time, which is 1024 sys- tem clock periods, to resume to the Green mode. This means that a dummy period is inserted after a Wake-up. If the Wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the Wake-up results in the next instruction execution, this will be executed im- mediately after the dummy period has finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the Sleep Mode or Idle Mode. The Sleep Mode or Idle Mode is initialised by a HALT in- struction and results in the following. · The system clock will be turned off. · The WDT function will be disabled if the WDT clock source is the instruction clock. · The WDT function will be disabled if the WDT clock source is the 32768Hz oscillator in the Idle mode. · The WDT will still function if the WDT clock source is the WDT internal oscillator. · If the WDT function is still enabled, the WDT counter and WDT prescaler will be cleared and resume count- ing. · The contents of the on chip Data Memory and regis- ters remain unchanged. · All the I/O ports maintain their original status. · The PDF flag is set and the TO flag is cleared by hard- ware. |
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