HT95R35 datasheet(18/73 Pages) HOLTEK

18 / 73 page

HT95R35

Rev. 1.00

October 7, 2009

grammer should check bit4~bit6 of MFIC1 to determine

the cause of the interrupt.

PFD Registers

- PFDC/PFDD

The device contains a Programmable Frequency Di-

vider function which can generate accurate frequencies

based on the system clock. The clock source, enable

function and output frequency is controlled using these

two registers.

RTCC Register

The device contains a Real Time Clock function other-

wise known as the RTC. To control this function a regis-

ter known as the RTCC register is provided which

provides the overall on/off control and time out flag.

DAC Register

- VOICEC/VOL/DAL/DAH

These four registers are for 12-bit DAC output data and

volume control.

Input/Output Ports

Holtek microcontrollers offer considerable flexibility on

their I/O ports. With the input or output designation of ev-

ery pin fully under user program control, pull-high op-

tions for all ports and wake-up options on certain pins,

the user is provided with an I/O structure to meet the

needs of a wide range of application possibilities. The

device provides 26 bidirectional input/output lines la-

beled with port names PA, PC, PD, PE, PF and PG.

These I/O ports are mapped to the Data Memory with

specific addresses as shown in the Special Purpose

Data Memory table. All of these I/O ports can be used

for input and output operations. For input operation,

these ports are non-latching, which means the inputs

must be ready at the T2 rising edge of instruction

²MOV

A,[m]

², where m denotes the port address. For output

operation, all the data is latched and remains un-

changed until the output latch is rewritten.

Unlike other port lines, PC2 and PC3 are supplied as

NMOS output-only lines. They have neither pull high op-

tion nor port control bit.

Pull-high Resistors

Many product applications require pull-high resistors for

their switch inputs usually requiring the use of an exter-

nal resistor. To eliminate the need for these external re-

sistors, all I/O pins, when configured as an input have

the capability of being connected to an internal pull-high

resistor. These pull-high resistors are selectable via

configuration options and are implemented using a

weak PMOS transistor.

Port A Wake-up

Each device has a HALT instruction enabling the

microcontroller to enter a Power Down Mode and pre-

serve power, a feature that is important for battery and

other low-power applications. Various methods exist to

wake-up the microcontroller, one of which is to change

the logic condition on one of the Port A pins from high to

low. After a

²HALT² instruction forces the

microcontroller into entering the Power Down mode, the

device will remain idle or in a low-power state until the

logic condition of the selected wake-up pin on Port A

changes from high to low. This function is especially

suitable for applications that can be woken up via exter-

nal switches. Note that each pin on Port A can be se-

lected individually to have this wake-up feature.

I/O Port Control Registers

Each I/O port has its own control register PAC, PCC,

PDC, PEC, PFC and PGC, to control the input/output

configuration. with this control register, each CMOS out-

put or input with or without pull-high resistor structures

can be reconfigured dynamically under software control.

Each pin of the I/O ports is directly mapped to a bit in its

associated port control register. For the I/O pin to func-

tion as an input, the corresponding bit of the control reg-

ister must be written as a

²1². This will then allow the

logic state of the input pin to be directly read by instruc-

tions. When the corresponding bit of the control register

is written as a

²0², the I/O pin will be setup as a CMOS

output. If the pin is currently setup as an output, instruc-

tions can still be used to read the output register. How-

ever, it should be noted that the program will in fact only

read the status of the output data latch and not the ac-

tual logic status of the output pin.

I/O Pin Structures

The following diagrams illustrate the I/O pin internal

structures. As the exact logical construction of the I/O

pin may differ from these drawings, they are supplied as

a guide only to assist with the functional understanding

of the I/O pins.

Programming Considerations

Within the user program, one of the first things to con-

sider is port initialization. After a reset, all of the I/O data

and port control registers will be set high. This means

that all I/O pins will default to an input state, the level of

which depends on the other connected circuitry and

whether pull-high options have been selected. If the port

control registers, PAC, PCC, PDC, PEC, PFC and PGC,

are then programmed to setup some pins as outputs,

these output pins will have an initial high output value

unless the associated port data registers, PA, PC, PD,

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

W r i t e t o P o r t

R e a d f r o m P o r t

S y s t e m C l o c k

P o r t D a t a

Read/Write Timing

HT95R35 Datasheet(PDF) 18 Page - Holtek Semiconductor Inc

HT95R35 Datasheet(HTML) 18 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Download

Link URL