HT95R35 datasheet(40/73 Pages) HOLTEK

40 / 73 page

HT95R35

Rev. 1.00

October 7, 2009

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests, the

following table shows the priority that is applied. These

can be masked by resetting the EMI bit.

Interrupt Source

All Devices Priority

Reset

External Interrupt

Timer 0 Interrupt

Timer 1 Interrupt

Peripheral Interrupt

Real Time Clock Interrupt

Multi-function Interrupt

In cases where both external and internal interrupts are

enabled and where an external and internal interrupt oc-

curs simultaneously, the external interrupt will always

have priority and will therefore be serviced first. Suitable

masking of the individual interrupts using the INTC reg-

ister can prevent simultaneous occurrences.

External Interrupt

For an external interrupt to occur, the global interrupt en-

able bit, EMI, and external interrupt enable bit, EEI, must

first be set. An actual external interrupt will take place

when the external interrupt request flag, EIF, is set, a situ-

ation that will occur when a high to low transition appears

on the INT line. When the interrupt is enabled, the stack is

not full and a high to low transition appears on the exter-

nal interrupt pin, a subroutine call to the external interrupt

vector at location 04H, will take place. When the interrupt

is serviced, the external interrupt request flag, EIF, will be

automatically reset and the EMI bit will be automatically

cleared to disable other interrupts.

Timer/Event Counter Interrupt

For a Timer/Event Counter interrupt to occur, the global

interrupt enable bit, EMI, and the corresponding timer

interrupt enable bit, ET0I or ET1I, must first be set. An

actual Timer/Event Counter interrupt will take place

when the Timer/Event Counter request flag, T0F or T1F,

is set, a situation that will occur when the Timer/Event

Counter overflows. When the interrupt is enabled, the

stack is not full and a Timer/Event Counter overflow oc-

curs, a subroutine call to the timer interrupt vector at lo-

cation 08H or 0CH, will take place. When the interrupt is

serviced, the timer interrupt request flag, T0F or T1F, will

be automatically reset and the EMI bit will be automati-

cally cleared to disable other interrupts.

Peripheral Interrupt

For a Peripheral interrupt to occur, the global interrupt

enable bit, EMI, and the corresponding peripehral inter-

rupt enable bit, EPERI, must first be set. An actual Pe-

ripheral interrupt will take place when the Peripheral

interrupt request flag, PERF, is set, a situation that will

occur when DTMF receiver detects a valid character.

When the interrupt is enabled, the stack is not full and a

Peripheral interrupt request occurs, a subroutine call to

the peripheral interrupt vector at location 10H, will take

place. When the interrupt is serviced, the peripheral in-

terrupt request flag, PERF, will be automatically reset

and the EMI bit will be automatically cleared to disable

other interrupts.

Real Time Clock Interrupt

For a Real Time Clock interrupt to occur, the global inter-

rupt enable bit, EMI, and the corresponding real timer

clock interrupt enable bit, ERTCI, must first be set. An

actual Real Time Clock interrupt will take place when the

Real Time Clock request flag, RTCF, is set, a situation

that will occur when the RTC times out which will occur

every second. When the interrupt is enabled, the stack

is not full and a Real Time Clock interrupt request oc-

curs, a subroutine call to the real time clock interrupt

vector at location 14H, will take place. When the inter-

rupt is serviced, the timer interrupt request flag, RTCF,

will be automatically reset and the EMI bit will be auto-

matically cleared to disable other interrupts.

Multi-function Interrupt

For a Multi-function interrupt to occur, the global inter-

rupt enable bit, EMI, and the corresponding

multi-function interrupt enable bit, EMFI, must first be

set. An actual Multi-function interrupt will take place

when the Multi-function interrupt request flag, MFF, is

set, a situation that will occur when PC0 or PC5 has a

falling edge, or PC7 has a rising edge, a SPI/I

2C inter-

rupt, an external peripheral has a falling edge or a timer2

overflow ossurs. When the interrupt is enabled, the

stack is not full and a Multi-function interrupt request oc-

curs, a subroutine call to the multi-function interrupt vec-

tor at location 18H, will take place. When the interrupt is

serviced, the multi-function interrupt request flag, MFF,

will be automatically reset and the EMI bit will be auto-

matically cleared to disable other interrupts.

HT95R35 Datasheet(PDF) 40 Page - Holtek Semiconductor Inc

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