PixArt Imaging Inc.

PAC107

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PixArt Imaging Inc.

V1.4, Aug, 2005

(0, 0) => Default

(0, 1) => PAC107’s system clk/2

(1, 0) => PAC107’s system clk/4

(1, 1) => PAC107’s system clk/8

CKCON

Address: 8Eh

bit 7

bit 0

WDT1

WDT0

T2M

T1M

T0M

MD2

MD1

MD0

Clock Control register

WDT1, WDT0: WDT time-out counter select

0, 0 - 17 bit counter

0, 1 - 20 bit counter

1, 0 - 23 bit counter

1, 1 - 26 bit counter

T2M:

Timer2 clock = sysclk/4(T2M=1) or sysclk/12(T2M=0)

T1M:

Timer1 clock = sysclk/4(T2M=1) or sysclk/12(T2M=0)

T0M:

Timer0 clock = sysclk/4(T2M=1) or sysclk/12(T2M=0)

MD2, MD1, MD0: Insert Wait-state of MOVX

(0, 0, 0): No Wait-State

(0, 0, 1): Original + 4T

(0, 1, 0): Original + 8T

(0, 1, 1): Original + 12T

(1, 0, 0): Original + 16T

(1, 0, 1): Original + 20T

(1, 1, 0): Original + 24T

(1, 1, 1): Original + 28T

SCON1

Address: C0H

bit 7

bit 0

SM0_1/FE_1

SM1_1

SM2_1

REN_1

TB8_1

RB8_1

TI_1

RI_1

SCON_1 register

FE_1: Framing Error Bit.

Set by receiver when an invalid stop bit is detected. The FE is not cleared by valid

frames but should be clear by software. The "SMOD0" must be set to enable access

to the FE bit.