HT95R64 datasheet(59/82 Pages) HOLTEK

59 / 82 page

HT95R64/HT95R65

Rev. 1.00

March 3, 2010

FSK Decoder

The FSK decoder supports four interrupt sources to the

peripheral interrupt vector, which are FSK raw data fall-

ing edge, ring detect or line reversal detect, FSK carrier

detect and FSK packet data. Write

²1² to the control flag

EFSKDI in PERIC register, or write

²0² to the control

flags, RMSK, CMSK and FMSK in FSKC register, will

enable these interrupts. When any of these interrupts

occurs, its interrupt flag (FSKDF in PERIC register;

RDETF, CDETF, and FSKF in FSKS register) will be set

to 1 by hardware even if the interrupt is disabled. These

interrupts will cause a peripheral interrupt if the periph-

eral interrupt is enabled. When the peripheral interrupt

occurs, the interrupt request flag PERF will be set and a

subroutine call to location 10H will occur. Returning from

the interrupt subroutine, the interrupt flag FSKDF,

RDETF, CDETF or FSKF will not be cleared by hard-

ware, the user should clear it by software. If interrupt

flag RDETF is not cleared, next ring detect interrupt will

be inhibited, other interrupt flags CDETF, FSKF, FSKDF

have the same behavior. The Power Down Mode

(F_PWDN=1) will terminate all the FSK decoder func-

tion, however, the registers FSKC, FSKS and FSKD are

accessible at this Power Down Mode.

Care must be taken with FSK raw data falling edge inter-

rupt. If the EFSKDI is enabled, then that will disable the

RMSK, CMSK and FMSK interrupts. The designer

should take care the software design flow to decoder the

FSK signals.

Ring or Line Reversal Detect

When no signal is present on the telephone line, RDET

will be at GND and RTIME is pulled to VDD by R1. If a

line reversal occurs, the RDET1 pin will become high.

This causes RTIME and internal signal R_DET to be

pulled low. The C1 and R1 ensure that the R_DET signal

is low during such a time, so that processor can detect it.

When a ring occurs on the line, internal signal R_DET is

permanently low, indicating the envelope of the ring. If

the frequency of the ring must be measured, C1 may be

removed, RTIME and R_DET inverter follow RDET. The

flag RDETF will go high when the R_DET signal falling

edge is detected. This may cause a peripheral interrupt

if RMSK is

²0² and the peripheral interrupt is enabled

(EPERI=1).

FSK Data Output

The FSK decoder will decode the FSK signal on the TIP

and RING line and produce two kinds of data formats,

the serial data and the 8-bit packet data. It also provides

the FSK carrier detection signal. To enable the FSK de-

coder, the F_PWDN should be written as

²0². Once the

FSK carrier signal is detected, the flag CDETF will be

set to

²1². This may cause a peripheral interrupt if CMSK

²0² and the peripheral interrupt is enabled. The serial

FSK data is present in two formats: RAW data and

COOK data, and could be monitored by the flag DOUT,

DOUTC, respectively. The flag DOUT presents the out-

put of the decoder when the decoder is at operation

mode. This data stream includes the alternate 1 and 0

patterns, the marking and the data. The flag DOUTC

presents the output of the decoder when the decoder is

at operation mode. This data stream is like the DOUT

flag but does not include the alternate 1 and 0 patterns.

If the FSK data is not detected, the DOUT and DOUTC

are held high. User can use the FSK raw data falling

edge interrupt with DOUT flag and a timer to implement

data decoding by software or by the build-in decoding

hardware which is described next.

Beside the serial data, the decoder also provides FSK

packet data. When decoder receives an FSK signal, it

will packet 10 bits data to 8 bits data, the first and 10th

bits will be discarded. When the 8-bit packet data is

valid, it will be stored in the FSK data register FSKD, the

FSK packet data interrupt flag FSKF will be set to

²1².

This may cause a peripheral interrupt if FMSK is

²0² and

the peripheral interrupt is enabled. The FSK packet

source could be DOUT or DOUTC, selected by

FSKSEL. Note that the start bit of the 10 packet bit

should be

²0², so the MARK signal (one of the FSK data

signals) will not be packeted.

To detect the carrier signal or decode the serial data or

packet 10-bit data to 8-bit data, the operation mode of

the controller must be selected in Normal mode. When

the operation mode is Green or Sleep, FSK decoder will

decode the wrong signal. However, when the operation

mode is Green or Sleep mode and the FSK decoder is at

power down mode (F_PWDN=1), the ring and line re-

versal detect is still functional.

HT95R64 Datasheet(PDF) 59 Page - Holtek Semiconductor Inc

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