HT95R64 datasheet(19/82 Pages) HOLTEK

19 / 82 page

HT95R64/HT95R65

Rev. 1.00

March 3, 2010

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

· C is set if an operation results in a carry during an ad-

dition operation or if a borrow does not take place dur-

ing a subtraction operation; otherwise C is cleared. C

is also affected by a rotate through carry instruction.

· AC is set if an operation results in a carry out of the

low nibbles in addition, or no borrow from the high nib-

ble into the low nibble in subtraction; otherwise AC is

cleared.

· Z is set if the result of an arithmetic or logical operation

is zero; otherwise Z is cleared.

· OV is set if an operation results in a carry into the high-

est-order bit but not a carry out of the highest-order bit,

or vice versa; otherwise OV is cleared.

· PDF is cleared by a system power-up or executing the

²CLR WDT² instruction. PDF is set by executing the

²HALT² instruction.

· TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is set by a

WDT time-out.

In addition, on entering an interrupt sequence or execut-

ing a subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status registers are important and if the subroutine

can corrupt the status register, precautions must be

taken to correctly save it.

Interrupt Control Register

- INTC0, INTC1

These two 8-bit register, known as the INTC0 and

INTC1 registers, control the operation of all interrupts.

By setting various bits within this register using standard

bit manipulation instructions, the enable/disable func-

tion of the external and timer interrupts can be inde-

pendently controlled. A master interrupt bit within this

and is used to set all of the interrupt enable bits on or off.

This bit is cleared when an interrupt routine is entered to

disable further interrupt and is set by executing the

²RETI² instruction.

Timer/Event Counter Registers

This device contains three 16-bit Timer/Event Counters,

which have associated register pairs known as TMR0L/

TMR0H, TMR1L/TMR1H and TMR2L/TMR2H. These

are the locations where the timers 16-bit value is lo-

cated. Three associated control registers, known as

TMR0C, TMR1C and TMR2C, contain the setup infor-

mation for these three timers.

Input/Output Ports and Control Registers

Within the area of Special Function Registers, the I/O

registers and their associated control registers play a

prominent role. All I/O ports have a designated register

correspondingly labeled as PA, PC, PD, PE and PF.

These labeled I/O registers are mapped to specific ad-

dresses within the Data Memory as shown in the Data

Memory table, which are used to transfer the appropri-

ate output or input data on that port. With each I/O port

there is an associated control register labeled PAC,

PCC, PDC, PEC and PFC, also mapped to specific ad-

dresses with the Data Memory. Except PC2 and PC3,

the control register specifies which pins of that port are

set as inputs and which are set as outputs. PC2 or PC3

are NMOS outputs, so the corresponding bits of the con-

trol register are not implemented. To setup a pin as an

input, the corresponding bit of the control register must

be set high and for an output it must be set low. During

program initialisation, it is important to first setup the

control registers to specify which pins are outputs and

which are inputs before reading data from or writing data

to the I/O ports. One flexible feature of these registers is

the ability to directly program single bits using the

²SET

[m].i

² and ²CLR [m].i² instructions. The ability to change

I/O pins from output to input and vice versa by manipu-

lating specific bits of the I/O control registers during nor-

mal program operation is a useful feature of these

devices.

DTMF Registers

- DTMFC, DTMFD, DTRXC, DTRXD

The device contains a fully integrated DTMF receiver and

generator circuitry for decoding and generation of DTMF

signals. The DTMF receiver requires two registers to

control its operation, a DTRXC control register to control

its overall function and a DTRXD register to store the

DTMF decoded signal data. The DTMF generator also

requires two registers for its operation, a DTMFC register

for its overall control and DTMFD register to store the dig-

ital codes that are to be generated as DMTF signals.

FSK Registers

- FSKC, FSKS, FSKD, PERIC

The device contains a fully integrated FSK decoder. The

FSK interrupt function is controlled by two registers,

PERIC and FSKC. The FSKS register is for the designer

to check the interrupt status and a FSKD resister to

store the decoded FSK cooked data.

Mode Register

- MODE, MODE_1

The device supports two system clocks and four opera-

tion modes. The system clock can be ether a low

frequency 32768Hz oscillator or a high frequency HCLK

oscillator. The operation modes can be either Normal,

Green, Sleep or Idle. These are all selected using soft-

ware. MODE_1 register supports four high frequency

clocks (HCLK) for the MCU which are 3.58MHz,

7.16MHz, 10.74MHz and 14.32 MHz.

MFIC Register

- MFIC0

PC0, PC5 and PC7 can be used to trigger an extra inter-

rupt. They are enabled or disabled individually by

bit0~bit2 of MFIC0. When a multi-function interrupt oc-

HT95R64 Datasheet(PDF) 19 Page - Holtek Semiconductor Inc

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