WM8148 datasheet(12/43 Pages) WOLFSON

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WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

PARALLEL INTERFACE

STB

DNA

RNW

D[11:4]

DATA IN

ADDRESS IN

ADC DATA OUT

DATA OUT

ADC DATA OUT

STB

ASU

DSU

STDO

STAO

ADLS

ADLH

ADHS

ADHH

OPD

OPZ

Figure 8 Parallel Interface Timing

TEST CONDITIONS

AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70

°C, MCLK = 48MHz unless

otherwise stated (AVDD denotes the voltage applied to all AVDD pins).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

RNW Low to OP[11:4] Hi-Z.

tOPZ

Address set-up time to STB Low

tASU

DNA Low set-up time to STB Low

tADLS

Strobe Low time

tSTB

Address hold time from STB High

tAH

DNA Low hold time from STB High

tADLH

Data set-up time to STB Low

tDSU

DNA High set-up time to STB Low

tADHS

Data hold time from STB High

tDH

Data High hold time from STB High

tADHH

RNW High to OP[11:4] output

tOPD

Data output propagation delay from

STB Low

tSTDO

ADC data out propagation delay

from STB High

tSTAO

Note:

Parameters are measured at 50% of the rising/falling edge.

WM8148 Datasheet(PDF) 12 Page - Wolfson Microelectronics plc

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