P89LPC915FDH datasheet(41/75 Pages) NXP

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P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

41 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

The clock source for this counter can be either the CPU clock (CCLK) or the external clock

input, provided that the external clock input is not being used as the CPU clock. If the

external clock input is used as the CPU clock, then the RTC will use CCLK as its clock

source. Only power-on reset will reset the RTC and its associated SFRs to the default

state.

8.19 UART

The P89LPC915/916/917 has an enhanced UART that is compatible with the conventional

80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source. The

P89LPC915/916/917 does include an independent Baud Rate Generator. The baud rate

can be selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the

independent Baud Rate Generator. In addition to the baud rate generation, enhancements

over the standard 80C51 UART include Framing Error detection, automatic address

recognition, selectable double buffering and several interrupt options. The UART can be

operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU

clock/16.

8.19.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at 1

⁄

16 of the CPU clock

frequency.

8.19.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),

8 data bits (LSB ﬁrst), and a stop bit (logic 1). When data is received, the stop bit is stored

in RB8_n in Special Function Register SnCON. The baud rate is variable and is

determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in Section

8.19.5 “Baud rate generator and selection”).

8.19.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data

bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic 1). When data is

transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of ‘0’ or ‘1’. Or, for

example, the parity bit (P, in the PSW) could be moved into TB8. When data is received,

the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not

saved. The baud rate is programmable to either 1

⁄16 or 1⁄32 of the CPU clock frequency, as

determined by the SMOD1 bit in PCON. The SMOD1 bit controls the Timer 1 output rate

available to the UART.

8.19.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8

data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is

the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable

and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in

Section 8.19.5 “Baud rate generator and selection”).

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