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P89LPC915FDH Datasheet(PDF) 56 Page - NXP Semiconductors |
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P89LPC915FDH Datasheet(HTML) 56 Page - NXP Semiconductors |
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56 / 75 page ![]() P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 15 December 2009 56 of 75 NXP Semiconductors P89LPC915/916/917 8-bit microcontrollers with accelerated two-clock 80C51 core 9.7 DAC output to a port pin with high output impedance The A/D converter’s DAC block can be output to a port pin. In this mode, the AD1DAT3 register is used to hold the value fed to the DAC. After a value has been written to the DAC (written to AD1DAT3), the DAC output will appear on the channel 3 pin. 9.8 Clock divider The A/D converter requires that its internal clock source be in the range of 500 kHz to 3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose. 9.9 Power-down and Idle mode In Idle mode the A/C converter, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is enabled, it will consume power. Power can be reduced by disabling the A/D. |
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