P89LPC915FDH datasheet(43/75 Pages) NXP

43 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

43 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

8.19.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long

as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until

the bit is shifted out, as indicated by the TI interrupt.

If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be

double-buffered together with SBUF data.

8.20 I2C-bus serial interface

I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected

to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves

• Multi master bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I2C-bus may be used for test and diagnostic purposes.

A typical I2C-bus conﬁguration is shown in Figure 14. The P89LPC915/916/917 device

provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.

Fig 14. I2C-bus conﬁguration

OTHER DEVICE

WITH I2C-BUS

INTERFACE

SDA

SCL

RPU

OTHER DEVICE

WITH I2C-BUS

INTERFACE

P1.3/SDA

P1.2/SCL

I2C MCU

I2C-bus

002aab410

P89LPC915FDH Datasheet(PDF) 43 Page - NXP Semiconductors

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