P89LPC915FDH datasheet(48/75 Pages) NXP

48 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

48 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

8.22 Analog comparators

Two analog comparators are provided on the P89LPC915/916/917. Input and output

options allow use of the comparators in a number of different conﬁgurations. Comparator

operation is such that the output is a logical one when the positive input is greater than the

negative input (selectable from a pin or an internal reference voltage). Otherwise the

output is a zero. Each comparator may be conﬁgured to cause an interrupt when the

output value changes. Comparator 1 may be output to a port pin.

The overall connections to both comparators are shown in Figure 20. The comparators

function to VDD = 2.4 V.

When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not

guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt

should not be enabled during that time, and the comparator interrupt ﬂag must be cleared

before the interrupt is enabled in order to prevent an immediate interrupt service.

8.22.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator input pin is used. The value of the internal reference voltage, referred to as

Vref(bg), is 1.23 V ± 10 %.

8.22.2 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag is

set whenever the comparator output changes state. The ﬂag may be polled by software or

may be used to generate an interrupt. The two comparators use one common interrupt

vector. If both comparators enable interrupts, after entering the interrupt service routine,

the user needs to read the ﬂags to determine which comparator caused the interrupt.

8.22.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is

activated, but both comparators are disabled automatically in Total Power-down mode.

Fig 20. Comparator input and output connections

comparator 1

CP1

CN1

(P0.4) CIN1A

(P0.3) CIN1B

(P0.5) CMPREF

Vref(bg)

OE1

change detect

CO1

CMF1

interrupt

002aaa904

CMP1 (P0.6)

change detect

CMF2

comparator 2

OE2

CO2

CMP2 (P0.0)

CP2

CN2

(P0.2) CIN2A

(P0.1) CIN2B

P89LPC915FDH Datasheet(PDF) 48 Page - NXP Semiconductors

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