MAC7200 datasheet(257/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

179

11.11.3.3 DTM Operation

11.11.3.3.1

Enabling Data Trace Messaging

Data Trace Messaging can be enabled in one of two ways.

•

Setting the TM field of the DC Register to enable Data Trace (DC[1]).

•

Using the DTS field of the WT Register to enable Data Trace on Watchpoint hits (ARM7

watchpoints are configured within the CPU).

11.11.3.3.2

DTM Queueing

A7S Nexus3 implements a programmable depth queue (32 minimum entry recommended) for queuing all

messages. Messages that enter the queue are transmitted via the auxiliary pins in the order in which they

are queued.

Table 11-40. Data Trace Exception Summary

Exception Condition

Exception Handling

System Reset Negation

At the negation of JTAG reset (TRST), queue pointers, counters, state machines, and

registers within the A7S Nexus3 module are reset. If Data Trace is enabled, the first

Data Trace Message is a Data Write/Read w/ Sync. Message.

Data Trace Enabled

The first Data Trace Message (after Data Trace has been enabled) is a synchronization

message.

Exit from Low Power/Debug

Upon exit from a Low Power mode or Debug mode the next Data Trace Message will be

converted to a Data Write/Read with Sync. Message.

Queue Overrun

An Error Message occurs when a new message cannot be queued due to the message

queue being full. The FIFO will discard messages until it has completely emptied the

queue. Once emptied, an Error Message will be queued. The error encoding will

indicate which type(s) of messages attempted to be queued while the FIFO was being

emptied. The next DTM message in the queue will be a Data Write/Read w/ Sync.

Message.

Periodic Data Trace Synchronization

A forced synchronization occurs periodically after 255 Data Trace Messages have been

queued. A Data Write/Read w/ Sync. Message is queued. The periodic data trace

message counter then resets.

Event In

If the Nexus module is enabled, an EVTI assertion initiates a Data Trace Write/Read w/

Sync. Message upon the next data write/read (if Data Trace is enabled and the EIC bits

of the DC Register have enabled this feature).

Attempted Access to Secure Memory For SOCs that implement security, any attempted read or write to secure memory

locations will temporarily disable Data Trace & cause the corresponding DTM to be lost.

A subsequent read/write will queue a Data Trace Read/Write w/ Sync. Message.

Collision Priority

Messages have the following priority: Error, Ownership Trace, Watchpoint, Debug,

Program Correlation, Branch Trace, Data Trace. A Data Trace message which attempts

to enter the queue at the same time as two other higher priority messages will be lost.

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