ADS58C48IPFPR datasheet(41/70 Pages) TI

41 / 70 page

79.5

80.5

81.5

82.5

66.5

66.6

66.7

66.8

66.9

67.1

67.2

67.3

THD

Input Clock Duty Cycle (%)

SNR

Fin = 20MHz

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

100

120

140

160

180

200

Sampling Frequency (MSPS)

AVDD = 1.8V

Fin = 2.5MHz

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

100

120

140

160

180

200

Sampling Frequency (MSPS)

Default after Reset

Digital Gain + Offset-Correction Enable

SNR Boost ON for 2ch’s (60MHz Filter)

SNR Boost ON for 4ch’s (60MHz Filter)

SNR Boost ON for 4ch’s + Digital Gain

+ Offset Correction

ADS58C48

www.ti.com

SLAS689 – MAY 2010

TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP

differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High Perf Mode disabled, 0 dB gain,

DDR LVDS output interface, 32k point FFT (unless otherwise noted)

PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE

Figure 40.

ANALOG POWER

DIGITAL POWER

SAMPLING FREQUENCY

Figure 41.

Figure 42.

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