ADS58C48IPFPR datasheet(12/70 Pages) TI

12 / 70 page

ADS58C48

SLAS689 – MAY 2010

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DEVICE CONFIGURATION

ADS58C48 has several modes that can be configured using a serial programming interface, as described below.

In addition, the device has three dedicated parallel pins for controlling common functions such as power down

and SNRBoost 3G control.

The functions controlled by each parallel pin are described below.

Table 4. PDN (Digital Control Pin)

VOLTAGE APPLIED

STATE OF REGISTER BIT

DESCRIPTION

ON PDN

Normal operation

HIGH

All channel ADCs are put in STANDBY mode (with internal references powered

down). This is an intermediate power down mode, with quick wake-up time.

HIGH

Device is put in global power down (all channel ADCs, references and output

buffers) drawing minimum power, with slow wake-up time.

Table 5. SNRB_1 (Digital Control Pin)

VOLTAGE APPLIED

DESCRIPTION

ON SNRB_1

LOW

SNRBoost 3G mode OFF for channels C and D

HIGH

SNRBoost 3G mode ON for channels C and D

Table 6. SNRB_2 (Digital Control Pin)

VOLTAGE APPLIED

DESCRIPTION

ON SNRB_2

LOW

SNRBoost 3G mode OFF for channels A and B

HIGH

SNRBoost 3G mode ON for channels A and B

SERIAL INTERFACE

The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN

(Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).

When SEN is low,

•

Serial shift of bits into the device is enabled.

•

Serial data (on SDATA pin) is latched at every falling edge of SCLK.

•

The serial data is loaded into the register at every 16th SCLK falling edge.

In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiple

of 16-bit words within a single active SEN pulse.

The first 8 bits form the register address and the remaining 8 bits are the register data. The interface can work

with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty

cycle.

After power-up, the internal registers MUST be initialized to their default values. This can be done in one of two

ways –

1. through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as shown

in Figure 6

2. By applying software reset. Using the serial interface, set the <RESET> bit (D1 in register 0x00) to HIGH.

This initializes internal registers to their default values and then self-resets the <RESET> bit to low. In this

case the RESET pin is kept low.

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