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ADS58C48IPFPR Datasheet(PDF) 57 Page - Texas Instruments |
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ADS58C48IPFPR Datasheet(HTML) 57 Page - Texas Instruments |
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57 / 70 page  S0442-01 CH X<0>_P/M CLKOUTP/M ADS58C48 11-Bit Data CH X<2>_P/M CH X<4>_P/M CH X<6>_P/M CH X<8>_P/M CH X<10>_P/M X = channels A, B, C, and D ADS58C48 www.ti.com SLAS689 – MAY 2010 DIGITAL OUTPUT INFORMATION ADS58C48 provides 11-bit digital data for each channel and a common output clock synchronized with the data. Output Interface Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be selected using the serial interface register bit <LVDS CMOS>. DDR LVDS Outputs In this mode, the data bits and clock are output using Low Voltage Differential Signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair. Figure 60. DDR LVDS Interface Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 57 Product Folder Link(s) :ADS58C48 |
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