ADS58C48IPFPR datasheet(24/70 Pages) TI

24 / 70 page

ADS58C48

SLAS689 – MAY 2010

www.ti.com

LVDS output clock buffer has double strength to be used with 50-

Ω external termination

<STBY>

Normal operation

All 4 channels are put in standby. Wake-up time from this mode is fast, typically 10 µsec

ADDRS

DEFAULT

A7-A0 IN

VALUE

HEX

AFTER

RESET

D7-D5

<OFFSET PEDESTAL – CH X> When the offset correction is enabled, the final converged value

after the offset is corrected will be the ADC mid-code value. A pedestal can be added to the final

converged value by programming these bits. Refer to the OFFSET CORRECTION section in

Application Information. Channels can be independently programmed for different offset pedestal by

choosing relevant register address.

011

PEDESTAL = 3 LSB

010

PEDESTAL = 2 LSB

001

PEDESTAL = 1 LSB

000

PEDESTAL = 0 LSB

111

PEDESTAL = –1 LSB

110

PEDESTAL = –2 LSB

101

PEDESTAL = –3 LSB

100

PEDESTAL = –4 LSB

ADDRS

DEFAULT

A7-A0 IN

VALUE

HEX

AFTER

RESET

<FREEZE

OFFSET

CORR>

<FREEZE OFFSET CORR> This bit sets the freeze offset correction.

Estimation of offset correction is not frozen (bit <EN OFFSET CORR> must be set)

Estimation of offset correction is frozen (bit <EN OFFSET CORR> must be set). When frozen, the

last estimated value is used for offset correction every clock cycle. Refer to the OFFSET

CORRECTION section.

D5-D2

<OFFSET CORR TIME CONSTANT> Offset correction loop time constant in number of clock

cycles. Refer to the OFFSET CORRECTION section.

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