TAS5616PHD datasheet(3/33 Pages) TI

3 / 33 page

TAS5616

www.ti.com

SLAS596B – JUNE 2009 – REVISED JANUARY 2010

MODE SELECTION PINS

MODE PINS

ANALOG

OUTPUT

DESCRIPTION

INPUT(1)

CONFIGURATION

2 × BTL

AD mode

—

Reserved

2 × BTL

BD mode

1 × BTL +2 × SE

AD mode

4 × SE

AD mode

INPUT_C(2)

INPUT_D(2)

1 × PBTL

AD mode

BD mode

Reserved

(1)

The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.

(2)

INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=AGND)..

PACKAGE HEAT DISSIPATION RATINGS

(1)

PARAMETER

TAS5616PHD

TAS5616DKD

RqJC (°C/W) – 2 BTL or 4 SE channels

3.63

2.52

RqJC (°C/W) – 1 BTL or 2 SE channel(s)

5.95

3.22

RqJC (°C/W) – 1 SE channel

9.9

6.9

Pad Area (2)

49 mm2

80 mm2

(1)

JC is junction-to-case, CH is case-to-heat sink

(2)

RqCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heat sink and

both channels active. The RqCH with this condition is 1.22°C/W for the PHD package and 1.02°C/W for the DKD package

Table 1. ORDERING INFORMATION(1)

PACKAGE

DESCRIPTION

0°C–70°C

TAS5616PHD

64 pin HTQFP

0°C–70°C

TAS5616DKD

44 pin PSOP3

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

Submit Documentation Feedback

Product Folder Link(s) :TAS5616

TAS5616PHD Datasheet(PDF) 3 Page - Texas Instruments

TAS5616PHD Datasheet(HTML) 3 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL