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LM8322 Datasheet(PDF) 29 Page - National Semiconductor (TI) |
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LM8322 Datasheet(HTML) 29 Page - National Semiconductor (TI) |
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29 / 42 page ![]() Please note: The data bytes which follow the command can be reads (toward the host) or writes (toward the LM8322). In the case of the READ_FIFO and RPT_READ_FIFO com- mands, the number of data bytes is variable, with the last transaction indicated by returning a negative acknowledge- ment (NACK). 17.1 READ_ID COMMAND The READ_ID command consists of a command byte (0x80) from the host and two data bytes from the LM8322. The first data byte returns the manufacturer code, and the second byte returns the device revision level. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 MANUFACTURER REVISION 17.2 WRITE_CFG COMMAND The WRITE_CFG command consists of a command byte (0x81) and a data byte from the host. The data byte is loaded into the hardware configuration register. The default state of this register is 0x80. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 1 IRQPST 0 0 0 MUX2EN MUX2SEL MUX1EN MUX1SEL Bit Value Description IRQPST 0 IRQ is an open-drain output. 1 IRQ is a push-pull output. MUX2EN 0 MUX2_OUT output disabled. 1 MUX2_OUT output enabled. This overrides any other function available on this pin. MUX2SEL 0 If the MUX2 EN bit is 1, the MUX2_IN1 input drives the MUX2_OUT output. 1 If the MUX2 EN bit is 1, the MUX2_IN2 input drives the MUX2_OUT output. MUX1EN 0 MUX1_OUT output disabled. 1 MUX1_OUT output enabled. This overrides any other function available on this pin. MUX1SEL 0 If the MUX1 EN bit is 1, the MUX1_IN1 input drives the MUX1_OUT output. 1 If the MUX1 EN bit is 1, the MUX1_IN2 input drives the MUX1_OUT output. Please note: The WRITE_CFG COMMAND defines basic hardware operation characteristics. It should be placed at the beginning of the initialization sequence driven from the host device after power on. It is not recommended to change the configuration during run time. Anytime this command is used, it initializes important operating characteristics such as the the GPIO port. This means that the GPIO pins must be re- established via WRITE_PORT_SEL and WRITE_PORT_STATE commands in this case. 29 www.national.com |
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