PPC8567CVTAUGGA datasheet(111/139 Pages) FREESCALE

111 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

111

Package and Pinout

Notes:

1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the local

bus controller section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2.

2. Recommend a weak pull-up resistor (2–10 K

Ω) be placed on this pin to OVDD.

4. This pin is an open drain signal.

5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the

reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k

Ω pull-down resistor. However, if the

signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset,

then a pullup or active driver is needed.

6. Treat these pins as no connects (NC) unless using debug address functionality.

7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k

Ω pull-up or pull-down

resistors. See Section 23.2, “CCB/SYSCLK PLL Ratio.”

8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-k

pull-up or pull-down resistors. See the Section 23.3, “e500 Core PLL Ratio.”

9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or

because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.

11.This output is actively driven during reset rather than being three-stated during reset.

12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.

13.These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking

and regulation.

14.Internal thermally sensitive resistor. These two pins are not ESD protected.

17.. The value of PA[0:4] during reset set the QE clock to SYSCLK PLL ratio. These pins require 4.7-k

Ω pull-up or pull-down

resistors. See Section 23.4, “QE/SYSCLK PLL Ratio.”

19. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state

during reset.

20. This pin is only an output in FIFO mode when used as Rx Flow Control.

24. Do not connect.

25.These are test signals for factory use only and must be pulled up (100 - 1 K) to OVDD for normal machine operation.

26. Independent supplies derived from board VDD.

27. Recommend a pull-up resistor (~1 K.) be placed on this pin to OVDD.

29. The following pins must NOT be pulled down during power-on reset: HRESET_REQ, TRIG_OUT/READY/QUIESCE,

MSRCID[2:4], ASLEEP, PA[5]

Table 78. MPC8568E Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power

Supply

Notes

PPC8567CVTAUGGA Datasheet(PDF) 111 Page - Freescale Semiconductor, Inc

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