PPC8567CVTAUGGA datasheet(112/139 Pages) FREESCALE

112 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

112

Freescale Semiconductor

Package and Pinout

Table 79 provides the pin-out listing for the MPC8567E 1023 FC-PBGA package.

30. This pin requires an external 4.7-k

Ω pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively

driven.

33. PF[21:22] are multiplexed as cfg_dram_type[0:1]. THEY MUST BE VALID AT POWER-UP, EVEN BEFORE HRESET

ASSERTION.

35. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled

down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the PCIn_AD pins as "No

Connect" or terminated through 2–10 K

Ω pull-up resistors with the default of internal arbiter if the PCIn_AD pins are not

connected to any other PCI device. The PCI block will drive the PCIn_AD pins if it is configured to be the PCI arbiter—through

POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any

other PCI device connected on the bus.

36.MDIC[0] is grounded through an 18.2-

Ω precision 1% resistor and MDIC[1] is connected to GVDD through an 18.2-Ω precision

1% resistor. These pins are used for automatic calibration of the DDR IOs.

39. If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCI_CLK . Otherwise the processor

will not boot up.

41.These pins should be tied to SCOREGND through a 300 ohm resistor if the high speed interface is used.

43. It is highly recommended that unused SD_RX/SD_RX lanes should be powered down with lane_x_pd. Otherwise the

receivers will burn extra power and the internal circuitry may develop long term reliability problems.

44. See Section 25.9, “Guidelines for High-Speed Interface Termination.”

46. Must be high during HRESET. It is recommended to leave the pin open during HRESET since it has internal pullup resistor.

47. Must be pulled down with 4.7-k

Ω resistor.

48. This pin must be left no connect.

49. A pull-up on LGPL4 is required for systems that boot from local bus (GPCM)-controlled NOR Flash.

Table 79. MPC8567E Pinout Listing

Signal

Package Pin Number

Pin Type

Power

Supply

Notes

PCI

PCI_AD[31:0]

AE19, AG20, AF19, AB20, AC20, AG21, AG22,

AB21, AF22, AH22, AE22, AF20, AB22, AE20,

AE23, AJ23, AJ24, AF27, AJ26, AE29, AH24,

AD24, AE25, AE26, AH27, AG27, AJ25, AE30,

AF26, AG26, AF28, AH26

I/O

OVDD

—

PCI_C_BE[3:0]

AC22, AD20, AE28, AH25

I/O

OVDD

—

PCI_GNT[4:1]

AF29, AB18, AC18, AD18

OVDD

5,9,35

PCI_GNT0

AE18

I/O

OVDD

—

PCI_IRDY

AF23

I/O

OVDD

PCI_PAR

AJ22

I/O

OVDD

—

PCI_PERR

AF24

I/O

OVDD

PCI_SERR

AD22

I/O

OVDD

2,4

PCI_STOP

AE24

I/O

OVDD

PCI_TRDY

AK24

I/O

OVDD

Table 78. MPC8568E Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power

Supply

Notes

PPC8567CVTAUGGA Datasheet(PDF) 112 Page - Freescale Semiconductor, Inc

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