PPC8567CVTAUGGA datasheet(136/139 Pages) FREESCALE

136 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

136

Freescale Semiconductor

Ordering Information

•SD_TX[7:0]

25.9.2

Unused input

25.9.2.1

SerDes block power not supplied

If the high speed interface is not used at all, then SCOREVDD/XVDD/AVDD_SRDS can be tied to GND,

all receiver inputs should be tied to the GND as well. This includes:

•SD_RX[7:0]

•SD_REF_CLK

•

SD_REF_CLK

•

SD_RX_CLK

•

SD_RX_FRM_CTL

25.9.2.2

SerDes Interface Partly used

If the high-speed SerDes interface is partly unused, any of the unused receiver pins should be terminated

as follows:

•

SD_RX[7:0] = tied to SCOREGND

•SD_RX[7:0] = tied to SCOREGND

•

SD_REF_CLK = tied to SCOREGND

•SD_REF_CLK = tied to SCOREGND

NOTE

Power down the unused lane through SERDESCR1[0:7] register

(offset = 0xE_0F08) (This prevents the oscillations and holds the receiver

output in a fixed state.) that maps to SERDES lane 0 to lane 7 accordingly.

During HRESET/POR, the high-speed interface must be in Serial RapidIO mode and/or PCI Express mode

according to the state of the PE[8:10]. Software must disable this mode through DEVDISR[SRIO] or

DEVDISR[PCIE] accordingly during software initialization.

26 Ordering Information

Contact your local Freescale sales office or regional marketing team for order information.

PPC8567CVTAUGGA Datasheet(PDF) 136 Page - Freescale Semiconductor, Inc