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MM912F634CV2AP Datasheet(PDF) 33 Page - Freescale Semiconductor, Inc |
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MM912F634CV2AP Datasheet(HTML) 33 Page - Freescale Semiconductor, Inc |
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33 / 335 page  Electrical Characteristics Dynamic Electrical Characteristics MM912F634 Freescale Semiconductor 33 Table 43 lists the timing characteristics for master mode. Table 43. SPI Master Mode Timing Characteristics Characteristic Symbol Min Typ Max Unit SCK frequency fSCK 1/2048 - 1 /2fBUS SCK period tSCK 2.0 - 2048 tBUS Enable lead time tLEAD -1/2 - tSCK Enable lag time tLAG -1/2 - tSCK Clock (SCK) high or low time tWSCK -1/2 - tSCK Data setup time (inputs) tSU 8.0 - - ns Data hold time (inputs) tHI 8.0 - - ns Data valid after SCK edge tVSCK - - 29 ns Data valid after SS fall (CPHA = 0) tVSS - - 15 ns Data hold time (outputs) tHO 20 - - ns Rise and fall time inputs tRFI -- 8.0 ns Rise and fall time outputs tRFO -- 8.0 ns |
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