MM912F634CV2AP datasheet(92/335 Pages) FREESCALE

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Functional Description and Application Information

PWM Control Module (PWM8B2C)

MM912F634

Freescale Semiconductor

4.13.3.3

PWM Scale A Register (PWMSCLA)

NOTE

When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A

is thus divided by 512.

PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock

A, dividing it by the value in the PWMSCLA register and dividing that by two.

Clock SA = Clock A / (2 * PWMSCLA)

Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA)

4.13.3.4

PWM Scale B Register (PWMSCLB)

NOTE

When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B

is thus divided by 512.

PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated by taking clock

B, dividing it by the value in the PWMSCLB register and dividing that by two.

Clock SB = Clock B / (2 * PWMSCLB)

Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB).

Table 115. Clock A Prescaler Selects

PCKA2

PCKA1

PCKA0

Value of Clock A

D2D clock

D2D clock / 2

D2D clock / 4

D2D clock / 8

D2D clock / 16

D2D clock / 32

D2D clock / 64

D2D clock / 128

Table 116. PWM Scale A Register (PWMSCLA)

Offset(82) 0x62

Access: User read/write

543

210

Bit 7

Bit 0

Reset

000

Note:

82. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

MM912F634CV2AP Datasheet(PDF) 92 Page - Freescale Semiconductor, Inc

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