IMX53AEC datasheet(21/178 Pages) FREESCALE

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Electrical Characteristics

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2

Freescale Semiconductor

TVDAC_DHVDD7

TVDAC_AHVDDRGB7

TVE digital and analog power supply, TVE-to-DAC

level shifter supply, cable detector supply, analog

power supply to RGB channel

2.69

2.75

2.91

For GPIO use only, when TVE is not in use

1.65

1.8 or

2.775

3.1

NVCC_SRTC_POW

SRTC Core and slow I/O Supply (GPIO)8

1.25

1.3

1.35

NVCC_RESET

LVIO

1.65

1.8 or

2.775

3.1

USB_H1_VDDA25

USB_OTG_VDDA25

NVCC_XTAL

USB_PHY analog supply, oscillator amplifier analog

supply9

2.25

2.5

2.75

USB_H1_VDDA33

USB_OTG_VDDA33

USB PHY I/O analog supply

3.0

3.3

3.6

VBUS

See Table 4 on page 18 and Table 106 on page 148

for details. Note that this is not a power supply.

——

—

VDD_REG10

Power supply input for the integrated linear

regulators

2.37

2.5

2.63

SATA PHY core power supply

1.25

1.3

1.35

VPH

SATA PHY I/O supply voltage

2.25

2.5

2.75

Junction Temperature

–40

10511

125

1 Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design

must allow for supply tolerances and system voltage drops.

2 The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV. Use of supplies with a

tighter tolerance allows reduction of the setpoint with commensurate power savings.

3 VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections. When operating in this

configuration, the regulator is still operating at the default 1.2 V, as bootup start. During bootup initialization, software should

increase this regulator voltage to match VCC (1.3 V nominal) in order to reduce internal leakage current.

4 By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In this case, there is no need driving this

supply externally. LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass

capacitor of minimal value 22

μF should be connected to this pad in any case whether it is driven internally or externally. Use

of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.

5 By default, the VDD_ANA_PLL is driven from internal on-die 1.8 V linear regulator (LDO). In this case there is no need driving

this supply externally. A bypass capacitor of minimal value 22

μF should be connected to this pad in any case whether it is

driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.

6 After fuses are programmed, Freescale strongly recommends the best practice of reading the fuses to verify that they are

written correctly. In Read mode, VDD_FUSE should be floated or grounded. Tying VDD_FUSE to a positive supply (3.0 V–3.3

V) increases the possibility of inadvertently blowing fuses and is not recommended in read mode.

7 If not using TVE module or other pads in this power domain for the product, the TVDAC_DHVDD and TVDAC_AHVDDRGB

can remain floating.

8 GPIO pad operational at low frequency

9 The analog supplies should be isolated in the application design. Use of series inductors is recommended.

10 VDD_REG is power supply input for the integrated linear regulators of VDD_ANA_PLL and VDD_DIG_PLL when they are

configured to the internal supply option. VDDR_REG still has to be tied to 2.5 V supply when VDD_ANA_PLL and

VDD_DIG_PLL are configured for external power supply mode although in this case it is not used as supply source.

Table 6. i.MX53xA Operating Ranges (continued)

Symbol

Parameter

Minimum1 Nominal2 Maximum1

Unit

IMX53AEC Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

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