IMX53AEC datasheet(13/178 Pages) FREESCALE

13 / 178 page

Modules List

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2

Freescale Semiconductor

INTRAM

Internal RAM

Internal

Memory

Internal RAM, shared with VPU.

The on-chip memory controller (OCRAM) module, is an interface between

the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is

used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus.

BOOTROM

Boot ROM

Internal

Memory

Supports secure and regular boot modes.

The ROM controller supports ROM patching.

RTIC

Run-Time

Integrity Checker

Security

Protecting read only data from modification is one of the basic elements in

trusted platforms. The run-time integrity checker, version 3 (RTIC) block is

a data-monitoring device responsible for ensuring that the memory content

is not corrupted during program execution. The RTIC mechanism

periodically checks the integrity of code or data sections during normal OS

run-time execution without interfering with normal operation. The purpose

of the RTIC is to ensure the integrity of the peripheral memory contents,

protect against unauthorized external memory elements replacement and

assist with boot authentication.

SAHARA

Security

Accelerator

Security

SAHARA (symmetric/asymmetric hashing and random accelerator),

version 4, is a security coprocessor. It implements symmetric encryption

algorithms, (AES, DES, 3DES, RC4 and C2), public key algorithms (RSA

and ECC), hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256), and

a hardware true random number generator. It has a slave IP Bus interface

for the host to write configuration and command information, and to read

status information. It also has a DMA controller, with an AHB bus interface,

to reduce the burden on the host to move the required data to and from

memory.

SATA

Serial ATA

Connectivity

Peripherals

SATA HDD interface, includes the SATA controller and the PHY. It is a

complete mixed-signal IP solution for SATA HDD connectivity.

SCCv2

Security

Controller, ver. 2

Security

The security controller is a security assurance hardware module designed

to safely hold sensitive data, such as encryption keys, digital right

management (DRM) keys, passwords and biometrics reference data. The

SCCv2 monitors the system’s alert signal to determine if the data paths to

and from it are secure, that is, it cannot be accessed from outside of the

defined security perimeter. If not, it erases all sensitive data on its internal

RAM. The SCCv2 also features a key encryption module (KEM) that allows

non-volatile (external memory) storage of any sensitive data that is

temporarily not in use. The KEM utilizes a device-specific hidden secret key

and a symmetric cryptographic algorithm to transform the sensitive data

into encrypted data.

Table 2. i.MX53xA Digital and Analog Blocks (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

IMX53AEC Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc

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