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PCF2129A Datasheet(PDF) 21 Page - NXP Semiconductors |
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PCF2129A Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 69 page ![]() PCF2129A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 7 May 2010 21 of 69 NXP Semiconductors PCF2129A Integrated RTC, TCXO and quartz crystal 8.7 Reset function The PCF2129A has a Power-On Reset (POR) and a Power-On Reset Override (PORO) function implemented. 8.7.1 Power-On Reset (POR) The POR is active whenever the oscillator is stopped. The oscillator is also considered to be stopped during the time between power-on and stable crystal resonance (see Figure 10). This time may be in the range of 200 ms to 2 s depending on temperature and supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set logic 1). After POR, the following mode is entered: • 32.768 kHz CLKOUT active • Power-On Reset Override (PORO) available to be set • 24 hour mode is selected • Battery switch-over is enabled • Battery low detection is enabled The register values after power-on are shown in Table 4. 8.7.2 Power-On Reset Override (PORO) The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and therefore speed up on-board test of the device. Fig 10. Dependency between POR and oscillator 001aaf897 chip in reset chip not in reset t VDD oscillation internal reset Fig 11. Power-On Reset (POR) system 001aaj324 OSCILLATOR 0 = override inactive 1 = override active 0 = clear override mode 1 = override possible POR_OVRD SDA/CE SCL RESET OVERRIDE CLEAR osc stopped 0 = stopped, 1 = running reset |
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