PCF2129A_10 datasheet(32/69 Pages) NXP

32 / 69 page

PCF2129A_2

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Product data sheet

Rev. 02 — 7 May 2010

32 of 69

NXP Semiconductors

PCF2129A

Integrated RTC, TCXO and quartz crystal

• When the watchdog timer counter reaches 1, the watchdog timer flag WDTF (register

Control_2) is set logic 1

• When a minute or second interrupt occurs, the minute/second flag MSF (register

Control_2) is set logic 1 (see Section 8.12.1).

8.10.4 Pre-defined timers: second and minute interrupt

PCF2129A has two pre-defined timers which are used to generate an interrupt either once

per second or once per minute. The pulse generator for the minute or second interrupt

operates from an internal 64 Hz clock. It is independent of the watchdog timer. Each of

these timers can be enabled by the bits SI (second interrupt) and MI (minute interrupt) in

8.10.5 Clearing flags

The flags MSF, AF, and TSFx can be cleared by using the interface. To prevent one flag

being overwritten while clearing another, a logic AND is performed during the write

access. A flag is cleared by writing logic 0 whilst a flag is not cleared by writing logic 1.

Writing logic 1 will result in the flag value remaining unchanged.

Two examples are given for clearing the flags. Clearing a flag is made by a write

command:

• Bits labeled with - must be written with their previous values

• Bits labeled with T have to be written with logic 0

• WDTF is read only and has to be written with logic 0

Repeatedly re-writing these bits has no influence on the functional behavior.

Counter reached 1, WDTF is logic 1, and an interrupt is generated.

Fig 17. WD_CD set logic 1: watchdog activates an interrupt when timed out

001aag062

watchdog

timer value

WDTF

n = 1

MCU

INT

Table 33.

Flag location in register Control_2

Bit

Control_2

MSF

WDTF

TSF2

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