MSP430F167IPMR datasheet(56/77 Pages) TI

56 / 77 page

MSP430F15x, MSP430F16x, MSP430F161x

MIXED SIGNAL MICROCONTROLLER

SLAS368G − OCTOBER 2002 − REVISED MARCH 2011

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematics (continued)

port P3, P3.2, input/output with Schmitt trigger

P3.2/SOMI0

P3IN.2

Pad Logic

P3OUT.2

P3DIR.2

P3SEL.2

DCM_SOMI

SYNC

STE

STC

SO(MI)0

From USART0

(SO)MI0

To USART0

0: Input

1: Output

port P3, P3.3, input/output with Schmitt-trigger

P3.3/UCLK0/SCL

P3IN.3

Pad Logic

P3OUT.3

P3DIR.3

P3SEL.3

UCLK.0

DCM_UCLK

SYNC

STE

STC

From USART0

UCLK0

To USART0

0: Input

1: Output

NOTE: UART mode:

The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always

an input.

SPI, slave mode:

The clock applied to UCLK0 is used to shift data in and out.

SPI, master mode:

The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).

I2C, slave mode:

The clock applied to SCL is used to shift data in and out. The frequency of the clock source of the module must be

w 10 times the frequency of the SCL clock.

I2C, master mode:

To shift data in and out, the clock is supplied via the SCL terminal to all I2C slaves. The frequency of the clock source

of the module must be

w 10 times the frequency of the SCL clock.

MSP430F167IPMR Datasheet(PDF) 56 Page - Texas Instruments

MSP430F167IPMR Datasheet(HTML) 56 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL