GS9092ACNE3 datasheet(6/63 Pages) GENNUM

6 / 63 page

GS9092A GenLINX® III 270Mb/s Serializer for SDI and

DVB-ASI

Data Sheet

34715 - 4

May 2010

6 of 63

1.2 Pin Descriptions

Table 1-1: Pin Descriptions

Pin Number

Name

Timing

Type

Description

1LF-

Analog

Input

Loop filter component connection. Connect to LF+ through a

capacitor. See Typical Application Circuit on page 59.

PLL_GND

Analog

Input

Power

Ground connection for phase-locked loop. Connect to GND.

PLL_VDD

Analog

Input

Power

Power supply connection for phase-locked loop. Connect to +1.8V

DC.

CD_VDD

Analog

Input

Power

Power supply connection for serial digital cable driver. Connect to

+1.8V DC

5, 6SDO, SDO

Analog

Output

Serial digital differential output pair.

NOTE: these output signals will be forced into a mute state if RESET

is LOW.

CD_GND

Analog

Input

Power

Ground connection for serial digital cable driver. Connect to GND.

8NC

––

No connect.

9RSET

Analog

Input

An external 1% resistor connected between this input and CD_VDD

is used to set the SDO / SDO output amplitude.

VBG

Analog

Input

Bandgap filter capacitor. Connect as shown in the Typical

Application Circuit on page 59

SDO_EN

Non

Synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS / LVTTL compatible

Used to enable or disable the serial digital output.

When set LOW by the application layer, the serial digital output

signals SDO and SDO are muted.

When set HIGH by the application layer, the serial digital output

signals are enabled.

SDO and SDO outputs will also be high impedance when the RESET

pin is LOW.

GS9092ACNE3 Datasheet(PDF) 6 Page - Gennum Corporation

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