GS9092ACNE3 datasheet(23/63 Pages) GENNUM

23 / 63 page

GS9092A GenLINX® III 270Mb/s Serializer for SDI and

DVB-ASI

Data Sheet

34715 - 4

May 2010

23 of 63

The provided programmable multi-function I/O pins may be configured to input and

output various status signals including H, V, and F timing, a FIFO_FULL, and a

FIFO_EMPTY pulse. The internal FIFO supports 4 modes of operation, which may be

used for data delay, MPEG packet insertion, or ancillary data insertion.

Finally, the GS9092A contains a JTAG interface for boundary scan test implementations.

3.2 Parallel Data Inputs

Data inputs enter the device on the rising edge of either PCLK or WR_CLK, depending

on the configuration of the internal FIFO.

When the internal FIFO is bypassed or in ancillary data insertion mode (see Ancillary

Data Insertion Mode on page 31), data enters the device on the rising edge of PCLK as

shown in Figure 3-1. When the internal FIFO is configured for video mode, data enters

the device on the rising edge of WR_CLK (see Video Mode on page 26).

The input data format is defined by the setting of the external SMPTE_BYPASS and

DVB_ASI pins (Table 3-1). Input data must be presented in 10-bit format.

Figure 3-1: PCLK to Input Data Timing

NOTE: For a SMPTE compliant serial output, the jitter on the input PCLK across the

frequency spectrum should not exceed 350ps.

CONTROL

SIGNAL INPUT

DIN[9:0]

PCLK

50%

tIH

tSU

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

GS9092ACNE3 Datasheet(PDF) 23 Page - Gennum Corporation