GS9092ACNE3 datasheet(9/63 Pages) GENNUM

9 / 63 page

GS9092A GenLINX® III 270Mb/s Serializer for SDI and

DVB-ASI

Data Sheet

34715 - 4

May 2010

9 of 63

23, 25, 26STAT[2:0]

Synchronous

with PCLK or

WR_CLK

Input/

Output

MULTI FUNCTION I/O PORT

Signal levels are LVCMOS / LVTTL compatible.

Programmable multi-function I/O. By programming the bits in the

IO_CONFIG register, each pin can act as an output for one of the

following signals:

•H

•V

•F

• FIFO_FULL

• FIFO_EMPTY

Each pin may also act as an input for an external H, V, or F signal if

the DETECT_TRS pin is set LOW by the application layer

These pins are set to certain default values depending on the

configuration of the device and the internal FIFO mode selected.

See Programmable Multi-function I/O on page 51 for details.

24, 28, 42

IO_GND

Non

Synchronous

Input

Power

Ground connection for digital I/O. Connect to GND.

WR_CLK

Input

FIFO WRITE CLOCK

Signal levels are LVCMOS / LVTTL compatible.

The application layer clocks the parallel data into the device on the

rising edge of WR_CLK when the internal FIFO is configured for

video mode or DVB-ASI mode.

NOTE: If this pin is unused it should be pulled up to GND.

WR_RESET

Synchronous

with

WR_CLK

Input

FIFO WRITE RESET

Signal levels are LVCMOS / LVTTL compatible.

Valid input only when the device is in SMPTE mode (SMPTE_BYPASS

= HIGH, DVB-ASI = LOW) and the internal FIFO is configured for

video mode (Video Mode on page 26).

A HIGH to LOW transition will reset the FIFO write pointer to

address zero of the memory.

NOTE: If this pin is unused it should be pulled up to GND.

32 - 41

DIN[9:0]

Synchronous

with

WR_CLK

or PCLK

Input

PARALLEL VIDEO DATA BUS

Signal levels are LVCMOS / LVTTL compatible.

When the internal FIFO is enabled and configured for either video

mode or DVB-ASI mode, parallel data will be clocked into the

device on the rising edge of WR_CLK.

When the internal FIFO is in bypass mode, parallel data will be

clocked into the device on the rising edge of PCLK.

DIN9 is the MSB and DIN0 is the LSB.

PCLK

Input

PIXEL CLOCK INPUT

Signal levels are LVCMOS / LVTTL compatible.

27MHz parallel clock input.

RSV

–

Reserved. Do Not Connect.

Table 1-1: Pin Descriptions (Continued)

Pin Number

Name

Timing

Type

Description

GS9092ACNE3 Datasheet(PDF) 9 Page - Gennum Corporation

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