MCP3903 datasheet(30/54 Pages) MICROCHIP

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MCP3903

DS25048B-page 30

6.0

SERIAL INTERFACE

DESCRIPTION

6.1

OVERVIEW

The MCP3903 device is compatible with SPI modes

0,0 and 1,1. Data is clocked out of the MCP3903 on the

falling

edge of SCK, and data is clocked into the

MCP3903 on the rising edge of SCK. In these modes,

SCK can idle either high or low. Each SPI

communication starts with a CS falling edge and stops

with the CS rising edge. Each SPI communication is

independent. When CS is high, SDO is in high

impedance, and transitions on SCK and SDI have no

effect. Additional controls: RESET, DR are also

provided

separate

pins

for

advanced

communication. The MCP3903 interface has a simple

command structure. The first byte transmitted is always

the CONTROL byte that is 8 bits wide and is followed

by data bytes that are 24 bits wide. Both ADCs are

continuously converting data by default and can be

reset or shutdown through a CONFIG register setting.

Since each ADC data is either 16 or 24 bits (depending

on the WIDTH bits), the internal registers can be

grouped together with various configurations (through

the READ bits) in order to allow easy data retrieval

within only one communication. For device reads, the

internal address counter can be automatically incre-

mented in order to loop through groups of data within

the register map. The SDO will then output the data

located at the ADDRESS (A<4:0>) defined in the con-

trol byte and then ADDRESS+1 depending on the

READ<1:0> bits which select the groups of registers.

These groups are defined in Section 7.1 “ADC Chan-

nel Data Output Registers”

(Register Map). The Data

Ready pins (DRn) can be used as an interrupt for an

MCU and outputs pulses when new ADC channel data

is available. The RESET pin acts like a hard reset and

can reset the part to its default power-up configuration.

6.2

CONTROL BYTE

The control byte of the MCP3903 contains two device

address bits A<6:5>, 5 register address bits A<4:0>,

and a read/write bit (R/W). The first byte transmitted to

the MCP3903 is always the control byte.

FIGURE 6-1:

Control Byte.

The default device address bits are 01. A read on

undefined addresses will give an all zeros output on the

first and all subsequent transmitted bytes. A write on an

undefined address will have no effect and will not incre-

ment the address counter either.

The register map is defined in Section 7.1 “ADC

Channel Data Output Registers”

6.3

Reading from the Device

The first data byte read is the one defined by the

address given in the CONTROL byte. After this first

byte is transmitted, if CS pin is maintained low, the

communication continues and the address of the next

transmitted byte is determined by the status of the

READ bits in the STATUS/COM register. Multiple

looping configurations can be defined through the

READ<1:0> bits for the address increment (see 6.6

“SPI MODE 1,1 - Clock Idle High, Read/Write

Examples””

6.4

Writing to the Device

The first data byte written is the one defined by the

address given in the control byte. The write

communication automatically increments the address

for subsequent bytes. The address of the next

transmitted byte within the same communication (CS

stays low) is the next address defined on the register

map. At the end of the register map, the address loops

to the beginning of the register map. Writing a

non-writable register has no effect. SDO pin stays high

impedance during a write communication.

6.5

SPI MODE 0,0 - Clock Idle Low,

Read/Write Examples

In this SPI mode, the clock idles low. For the MCP3903,

this means that there will be a rising edge before there

is a falling edge.

A5 A4 A3 A2 A1 A0 R/W

Read

Write Bit

(0)

(1)

Address Bits

Device

Address Bits

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