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MCP3903 Datasheet(PDF) 17 Page - Microchip Technology |
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MCP3903 Datasheet(HTML) 17 Page - Microchip Technology |
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17 / 54 page ![]() © 2011 Microchip Technology Inc. DS25048B-page 17 MCP3903 4.0 TERMINOLOGY AND FORMULAS This section defines the terms and formulas used throughout this data sheet. The following terms are defined: MCLK - Master Clock AMCLK - Analog Master Clock DMCLK - Digital Master Clock DRCLK - Data Rate Clock OSR - Oversampling Ratio Offset Error Gain Error Integral Non-Linearity Error Signal-To-Noise Ratio (SNR) Signal-To-Noise Ratio And Distortion (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) MCP3903 Delta-Sigma Architecture Idle Tones Dithering Crosstalk PSRR CMRR ADC Reset Mode Hard Reset Mode (RESET = 0) ADC Shutdown Mode Full Shutdown Mode 4.1 MCLK - Master Clock This is the fastest clock present in the device. This is the frequency of the crystal placed at the OSC1/OSC2 inputs when CLKEXT = 0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT = 1. 4.2 AMCLK - Analog Master Clock This is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG PRESCALE<1:0> register bits. The analog portion includes the PGAs and the two sigma-delta modulators. EQUATION 4-1: 4.3 DMCLK - Digital Master Clock This is the clock frequency that is present on the digital portion of the device, after prescaling and division by 4. This is also the sampling frequency, that is the rate at which the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output. EQUATION 4-2: 4.4 DRCLK - Data Rate Clock This is the output data rate i.e. the rate at which the ADCs output new data. Each new data is signaled by a data ready pulse on the DR pin. This data rate is depending on the OSR and the prescaler with the following formula: EQUATION 4-3: TABLE 4-1: MCP3903 OVERSAMPLING RATIO SETTINGS Config Analog Master Clock Prescale PRE<1:0> 00 AMCLK = MCLK/ 1 (default) 01 AMCLK = MCLK/ 2 10 AMCLK = MCLK/ 4 11 AMCLK = MCLK/ 8 AMCLK MCLK PRESCALE ------------------------------- = DMCLK AMCLK 4 --------------------- MCLK 4 PRESCALE × ---------------------------------------- == DRC LK DMC LK OSR ---------------------- AMCLK 4OSR × --------------------- MCLK 4 OSR PRESCALE × × ----------------------------------------------------------- == = |
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