MCP3903 datasheet(4/54 Pages) MICROCHIP

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MCP3903

DS25048B-page 4

A011

CHn+-

Analog Input Absolute

Voltage

-1

All analog input channels,

measured to AGND

(Note 7)

A012

AIN

Analog Input Leakage

Current

1nA

(Note 4)

A013

(CHn+-

CHn-)

Differential Input Voltage

Range

500 /

GAIN

mVP

(Note 1)

A014

VOS

Offset Error

-3

(Note 6)(Note 2)

A015

Offset Error Drift

μV/C

From -40°C to 125°C

A016

Gain Error

-3

All Gains

A017

Gain Error Drift

—

ppm/°C From -40°C to 125°C

A018

INL

Integral Non-Linearity

ppm

GAIN = 1, DITHER = ON

A019

ZIN

Input Impedance

350

—

Proportional to 1/AMCLK

A020

SINAD

Signal-to-Noise and

Distortion Ratio

—

T = 25°C

81.5

A021

THD

Total Harmonic Distortion

-100

-97

OSR = 256, DITHER = ON;

(Note 2)(Note 3)

-90

-87

A022

SNR

Signal To Noise Ratio

91.5

T = 25°C

81.5

A023

SFDR

Spurious Free Dynamic

Range

102

OSR = 256, DITHER = ON;

(Note 2) (Note 3)

A024

CTALK

Crosstalk (50 / 60 Hz)

—

-115

—

OSR = 256, DITHER = ON;

(Note 2)(Note 3)

A025

AC PSRR AC Power Supply Rejection

—

-68

—

AVDD = 5V + 1Vpp @ 50 Hz

A026

DC PSRR DC Power Supply Rejection

—

-68

—

AVDD = 4.5 to 5.5V, DVDD =

3.3V

A027

CMRR

DC Common Mode Rejection

Ratio

—-75

—

VCM varies from -1V to +1V;

(Note 2)

Oscillator Input

TABLE 1-1:

ANALOG SPECIFICATIONS TARGET TABLE

(CONTINUED)

Electrical Specifications:

Unless otherwise indicated, all parameters apply at AVDD = 4.5 to 5.5V, DVDD = 2.7 to

3.6V, Internal VREF, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; fS = 1 MHz; fD = 15.625 ksps; TA = -40°C to +125°C,

GAIN = 1, VIN = 1VPP = 353mVRMS @ 50/60 Hz.

Param.

Num.

Symbol

Characteristic

Min.

Typ.

Max.

Units

Test Conditions

Note 1:

This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or

instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range,

VIN = -0.5 dBFS @ 50/60 Hz = 333 mVRMS, VREF = 2.4V.

See terminology section for definition.

This parameter is established by characterization and not 100% tested.

For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.

For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.

Applies to all gains. Offset error is dependant on PGA gain setting.

Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to

the part with no risk for damage.

For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits

off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a

crystal, CLKEXT bit should be equal to ‘0’.

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