MPC5125 datasheet(72/94 Pages) FREESCALE

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MPC5125 Microcontroller Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

4.3.12

CAN

The CAN functions are available as TX pins at normal IO pads and as RX pins at the VBAT domain. There is no filter for the

wakeup dominant pulse. Any high-to-low edge can cause wakeup, if configured.

4.3.13

I2C

This section specifies the timing parameters of the inter-integrated circuit (I2C) interface. Refer to the I2C bus specification.

Table 37. I2C Input Timing Specifications — SCL and SDA

Sym

Description

Min

Max

Units

SpecID

Start condition hold time

—

IP bus cycle1

NOTES:

1 Inter-peripheral clock is defined in the MPC5125 Reference Manual (MPC5125RM)

A18.1

Clock low time

—

IP bus cycle1

A18.2

Data hold time

0.0

—

A18.3

Clock high time

—

IP bus cycle1

A18.4

Data setup time

0.0

—

A18.5

Start condition setup time (for repeated start condition only)

—

IP bus cycle1

A18.6

Stop condition setup time

—

IP bus cycle1

A18.7

Table 38. I2C Output Timing Specifications — SCL and SDA 1

NOTES:

1 Output timing is specified at a nominal 50 pF load.

Sym

Description

Min

Max

Units

SpecID

2 Programming IFDR with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to

scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and

division values programmed in IFDR.

Start condition hold time

—

IP bus cycle3

3 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time that SCL or SDA

takes to reach a high level depends on external signal capacitance and pullup resistor values.

A18.8

Clock low time

—

IP bus cycle3

A18.9

4 Inter -peripheral Clock is defined in the MPC5125 Reference Manual (MPC5125RM).

SCL/SDA rise time

—

7.9

A18.10

Data hold time

—

IP bus cycle3

A18.11

SCL/SDA fall time

—

7.9

A18.12

Clock high time

—

IP bus cycle3

A18.13

Data setup time

—

IP bus cycle3

A18.14

Start condition setup time (for repeated start condition only)

—

IP bus cycle3

A18.15

Stop condition setup time

—

IP bus cycle3

A18.16

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