HT67F60 datasheet(124/242 Pages) HOLTEK

124 / 242 page

Rev. 1.50

124

March 06 , 2012

Rev. 1.50

125

March 06 , 2012

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO

Standard Type TM Operating Modes

The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,

PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The

operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register.

Compare Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In

this mode once the counter is enabled and running it can be cleared by three methods. These are a

counter overflow, a compare match from Comparator A and a compare match from Comparator P.

When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when

a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the

counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and

Comparator P respectively, will both be generated.

If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare

match occurs from Comparator A. However, here only the TnAF interrupt request flag will be

generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when

TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output

Mode, the CCRA can not be set to "0".

As the name of the mode suggests, after a comparison is made, the TM output pin, will change state.

The TM output pin condition however only changes state when an TnAF interrupt request flag is

generated after a compare match occurs from Comparator A. The TnPF interrupt request flag,

generated from a compare match occurs from Comparator P, will have no effect on the TM output

pin. The way in which the TM output pin changes state are determined by the condition of the

TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1

and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match

occurs from Comparator A. The initial condition of the TM output pin, which is setup after the

TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0

bits are zero then no pin change will take place.

10-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=0

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

128

256

384

512

640

768

896

1024

Duty

CCRA

If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 100b and CCRA = 128,

The STM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%

If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the

PWM output duty is 100%.

10-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=1

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

CCRA

Duty

128

256

384

512

640

768

896

1024

The PWM output period is determined by the CCRA register value together with the TM clock

while the PWM duty cycle is defined by the CCRP register value.

HT67F60 Datasheet(PDF) 124 Page - Holtek Semiconductor Inc

HT67F60 Datasheet(HTML) 124 Page - Holtek Semiconductor Inc

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