MMA8653FC datasheet(40/56 Pages) FREESCALE

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MMA8653FC

Sensors

Freescale Semiconductor, Inc.

6.8

Control registers

NOTE

Except for STANDBY mode selection, the device must be in STANDBY mode to change any

of the fields within CTRL_REG1 (0x2A).

6.8.1

0x2A: CTRL_REG1, System Control 1 Register

This register configures the Auto-WAKE sample frequency, data rate selection, and enables the fast read mode and STANDBY/

ACTIVE selection.

Figure 38. 0x2A: CTRL_REG1, System Control 1 Register (Read/Write)

DR[2:0] bits select the Output Data Rate (ODR) for acceleration samples in WAKE mode. The default value is 000 for a data

rate of 800 Hz.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ASLP_RATE1

ASLP_RATE0

DR2

DR1

DR0

F_READ

ACTIVE

Table 32. CTRL_REG1 register

Field

Description

ASLP_RATE[1:0]

Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode. Default value: 00.

See Table 33, “SLEEP Mode Rates".

DR[2:0]

Data rate selection. Default value: 000.

See Table 34, “System Output Data Rate Selection ".

F_READ

Fast Read mode: Data format limited to single Byte Default value: 0.

0: Normal mode

1: Fast Read mode

ACTIVE

STANDBY/ACTIVE selection. Default value: 00.

0: STANDBY mode

1: ACTIVE mode

Table 33. SLEEP Mode Rates

ASLP_RATE1

ASLP_RATE0

Frequency

(Hz)

Notes

When the device is in Auto-SLEEP mode, the system ODR and

the data rate for all the system functional blocks are overridden

by the data rate set by the ASLP_RATE field.

12.5

6.25

1.56

Table 34. System Output Data Rate Selection

DR2

DR1

DR0

ODR

Period

Notes

800 Hz

1.25 ms

default (STANDBY mode)

400 Hz

2.5 ms

200 Hz

5 ms

100 Hz

10 ms

50 Hz

20 ms

12.5 Hz

80 ms

6.25 Hz

160 ms

1.56 Hz

640 ms

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