TAS5721 datasheet(53/71 Pages) TI1

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ACK

Acknowledge

I CDevice Addressand

Read/WriteBit

R/W

R/W ACK

A0 ACK

ACK

Start

Condition

Stop

Condition

Acknowledge

LastDataByte

ACK

FirstDataByte

RepeatStart

Condition

Not

Acknowledge

I CDevice Addressand

Read/WriteBit

Subaddress

OtherDataBytes

D0 ACK

Acknowledge

T0036-04

A0 R/W ACK A7

A0 ACK

ACK

Start

Condition

Stop

Condition

Acknowledge

I CDevice Addressand

Read/WriteBit

Subaddress

DataByte

D0 ACK

I CDevice Addressand

Read/WriteBit

Not

Acknowledge

R/W

RepeatStart

Condition

T0036-03

TAS5721

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SLOS739 – JULY 2012

Single-Byte Read

As shown in Figure 64, a single-byte data read transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write

followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal

memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5721 address

and the read/write bit, TAS5721 responds with an acknowledge bit. In addition, after sending the internal memory

address byte or bytes, the master device transmits another start condition followed by the TAS5721 address and

the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the

address and the read/write bit, the TAS5721 again responds with an acknowledge bit. Next, the TAS5721

transmits the data byte from the memory address being read. After receiving the data byte, the master device

transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer.

Figure 64. Single-Byte Read Transfer

Multiple-Byte Read

A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes

are transmitted by the TAS5721 to the master device as shown in Figure 65. Except for the last data byte, the

master device responds with an acknowledge bit after receiving each data byte.

Figure 65. Multiple Byte Read Transfer

Output Mode and MUX Selection

The TAS5721 is a highly configurable device, capable of operating in 2.0, Single Device 2.1 and parallel bridge

tied load (PBTL) configurations. Addtionally, the modulation scheme can be changed for the channels to operate

either in AD or BD Modulation mode. While many configurations are possible because of this flexibility, the

majority of use cases uses will operate in one of the configurations shown below. For ease of use and reduced

complexity, the figure below outlines both the register settings and the output configurations required to set the

device up for operation in these various modes.

The output configuration quick reference table below highlights the controls that are required to configure the

device for various operational modes. Please note that other controls, which are not directly related to the output

configuration muxes may also be required. For example, the Inter Channel Delay (ICD) settings will likely need to

be modified to optimize for idle channel noise, cross-talk, and distortion performance for each of these

considerations, in addition to start and stop time and others. Please consult the respective registers for these

controls to optimize for various other peformance parameters and use cases.

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