TAS5721 datasheet(9/71 Pages) TI1

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w(RST)

RST

d(I2C_ready)

System Initialization.

Enable via I C.

T0421-01

I C Active

TAS5721

www.ti.com

SLOS739 – JULY 2012

I/O Pin Characteristics (continued)

PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application Circuit diagrams, and in

accordance with recommended operating conditions (unless otherwise specified).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Normal mode

3.3 V supply voltage (DVDD,

IDD

3.3 V supply current

Reset (RST = low, PDN

AVDD)

= high, DR_SD = low)

tw(RST)

Pulse duration, RST active

RST

100

μs

td(I2C_ready)

Time before the I2C port is able

communicate after RST goes

high

NOTE: On power up, it is recommended that the TAS5721 RST be held LOW for at least 100

μs after DVDD has reached 3

NOTE: If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100

μs after PDN is

deasserted (HIGH).

Figure 5. Reset Timing

Master Clock Characteristics

(1)

PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application Circuit diagrams, and in

accordance with recommended operating conditions (unless otherwise specified).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fMCLK

MCLK frequency

2.8224

24.576

MHz

MCLK duty cycle

40%

50%

60%

tr(MCLK) / tf(MCLK)

Rise/fall time for MCLK

(1)

For clocks related to the serial audio port, please see Serial Audio Port Timing

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