THS8083CPZP datasheet(17/61 Pages) TI1

17 / 61 page

2–3

Ext. Logic

PFD_FREEZE

THS8083

Frame Period

PFD_FREEZE High in VBI on Lines Where CS

Has Multiple Rising/Falling Edges Per Line

Option 1: Using PFD_FREEZE

Sync.

Separator

THS8083

Option 2: Using HS Derived From CS

PFD_FREEZE

Figure 2–4. Using THS8083 With a Composite Sync

Note that the slicer will only work when no video levels are lower than the blanking level and when the internal clamp

circuit is used. This is normally satisfied for G and Y channels, but not for U and V channels. To prevent unnecessary

toggling of the CS output signal, the CS output is switched off automatically when mid-level clamping is chosen for

channel 1 (i.e., CLP1_RG=1 in register <CLP_CTRL>). CS can be permanently disabled by setting CS_DIS=1 in

When CS is disabled, the CS output will be Hi-Z.

NOTE:

While PFD_FREEZE keeps the DTO output frequency constant, it does not disable the

phase/frequency detector (PFD) from internally updating its error value at every active edge

on HS. Therefore, when deasserting PFD_FREEZE and no external sync separator is used,

a discontinuity on the frequency increment to the DTO occurs which will cause an

instantaneous frequency shift. To prevent this, the user should gate the CS signal externally

with the PFD_FREEZE signal as shown in Figure 2.4. This will keep the PFD from updating

during PFD_FREEZE high, since HS will remain low during the VBI. By using both

PFD_FREEZE and gating during the vertical blanking interval, THS8083 can be locked to

signals with a composite sync.

To support sync-on-Y/sync-on-G extraction, the user should provide an external dc biasing to

the Y/G channel. This can be done by establishing a dc clamp through a diode with its cathode

connected to the ac-coupling capacitor (at the side of THS8083) on the AGY channel and

anode connected to a dc level. Since the slicing level is around 1.35 V and the sync amplitude

is ~300 mV, the negative sync-tip should be clamped by the diode to a level of approximately

1.2 V. For example, using a Schottky switching diode (type 1N5711) with a low forward voltage

drop of maximum 0.4 V, the dc level at the anode can be approximately 1.6 V. This level can

be derived through a resistive voltage divider off the power supply.

THS8083CPZP Datasheet(PDF) 17 Page - Texas Instruments