THS8083CPZP datasheet(51/61 Pages) TI1

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5–7

5.4.9.2 Closed Loop

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f(HS)

HS locking range

100

kHz

t(acq)

Lock-in time

Short term jitter

See Note 16

700 (p-p)

185 (rms)

t(JCS)

Short-term jitter

TA = 25°C

1250 (p-p)

440 (rms)

t(JCL)

Long term jitter

See Note 16

700 (pk-pk)

185 (rms)

t(JCL)

Long-term jitter

See Note 16

TA = 25°C

1250 (p-p)

440 (rms)

NOTE 16: PLL characterization:

•

Short term jitter in open loop or closed loop is defined as the variation within one PLL update period (= within the same video line) of

the clock rising edge. This is measured visually by capturing the clock and displaying it on a digital scope with a persistency of one

video line. Numerically the time instants of the rising edges, at a defined voltage level, of a number of clock cycles (N = 800) are

captured at high sampling rate. From these time instants, the average clock time period is calculated. The deviation between each

actual time instant and the ideal, based on the average clock time period, is defined as a statistically distributed jitter value along

one line. This jitter is measured on both DATACLK1 and DTOCLK3 outputs.

•

Long term jitter in closed loop is defined as the variation over one video frame of the Nth clock rising edge on each line. This is

measured by capturing the time instant that a defined level on the rising edge of the Nth clock after HS is reached on each line. The

same principle for calculation is used as for short term jitter but now for one sample taken on every line and N = 800 lines.

5.4.10 Typical Plots (25

°C and Measured for Standard VESA Graphics Formats)

NOTE: The THS8083 is configured for each video mode with I2C register settings as specified

in application note Using THS8083 for PC Graphics and Component Video Digitizing.

500

600

700

800

900

1000

1100

1200

1300

1400

1500

20406080

100

30 MHz Full-Scale

Sine Input

60 kHz Full-Scale

Ramp Input

100

150

200

250

300

350

100

Total Analog

AVDD_CH1+AVDD_CH2_3

Total Digital

AVDD_REF

DVDD

AVDD_PLL

f – Frequency – MHz

CURRENT

FREQUENCY

Figure 5–2. Power Consumption

DVDD_PLL

f – Frequency – MHz

POWER

FREQUENCY

THS8083CPZP Datasheet(PDF) 51 Page - Texas Instruments

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