THS8083CPZP datasheet(47/61 Pages) TI1

47 / 61 page

5–3

5.4

Electrical Characteristics Over Recommended Operating Free-Air Temperature

Range, TA = 0°C to 70°C (unless otherwise noted)

NOTE: In order to reach stated performance levels, the device’s PowerPad feature should be

thermally and electrically connected to the pcb ground plane, as described in section 6.1

Designing With PowerPadTM.

5.4.1

Power Supply

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog supply ( AVDD CH1 AVDD CH2 3 AVDD PLL AVDD REF)

ADC INTREF

275

340

Analog supply (=AVDD_CH1+AVDD_CH2_3+AVDD_PLL+AVDD_REF)

ADC_INTREF

275

340

Digital supply ( DVDD DVDD PLL)

ADC INTREF

110

125

Digital supply (=DVDD+DVDD_PLL)

ADC_INTREF

110

125

Total power dissipation normal operation

ADC INTREF

128

153

Total power dissipation normal operation

ADC_INTREF

1.28

1.53

Total power dissipation power down all modes

ADC PWDN

255

290

Total power dissipation, power down all modes

ADC_PWDN

255

290

5.4.2

Digital Logic Inputs (HS, VS, SCL, SDA, I2CA, XTL1_MCLK, EXT_ADCCLK, OE, RESET,

EXT_CLP)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level input current

–10

µA

IIL

Low-level input current

DVDD = 3.6 V,

Digital inputs and CLK at0Vfor I ;

–10

µA

IIL(CLK)

Low-level input current, CLK (see Note 6)

Digital inputs and CLK at 0 V for IIL;

Digital inputs and CLK at 3.6 V for IIH

–14

µA

IIH(CLK) High-level input current , CLK (see Note 6)

Digital in uts and CLK at 3.6 V for IIH

–14

µA

Input capacitance

NOTE 6: Applies to when XTL1_MCLK is driven by the clock signal directly.

5.4.3

Logic Outputs (SDA, CHn_OUTA[7..0], CHn_OUTB[7..0], DTOCLK3, ADCCLK2,

DATACLK1, DHS, LOCK)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

DVDD = 3 V at IOH = 50 µA,

Digital output forced high

2.9

VOL

Low-level output voltage

DVDD = 3.6 V at IOL = 50 µA,

Digital output forced low

0.15

Output capacitance

IOZ(H)/IOZ(L)†

High-impedance state output current

DVDD = 3.6 V

Worst-case for VO = 3.6 V and VO = 0 V

–10

µA

† Tested for CHn-OUTA[7..0] and CHn_OUTB[7..0] only

THS8083CPZP Datasheet(PDF) 47 Page - Texas Instruments

THS8083CPZP Datasheet(HTML) 47 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL