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THS8083CPZP Datasheet(PDF) 43 Page - Texas Instruments |
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THS8083CPZP Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 61 page  4–3 4.3 Timing Diagram – 48-Bit Interleaved Mode This mode allows a double-pixel width output interface with a 1 sampling clock period time offset between buses A and B. The DATACLK1 output is at half of the sampling clock frequency. DATACLK CH1_OUTA[7..0] CH2_OUTA[7..0] CH2_OUTB[7..0] CH1_OUTB[7..0] CH3_OUTA[7..0] CH3_OUTB[7..0] HS pix 01 01 03 02 04 pix 02 ADCCLK2 DHS 01 03 04 01 03 02 04 02 tPLH(OE) tPHL(OE) tsu(DHS) th(DHS) tsu(OUT) th(OUT) tsu(OUT) th(OUT) (DHS_POL = 0 Assumed-Inverted Polarity Otherwise) OE 7 ADCCLK2 Cycles Latency Last Samples From Previous Line Last Samples From Previous Line Last Samples From Previous Line Last Samples From Previous Line Last Samples From Previous Line Last Samples From Previous Line <DHS_MODE> = 1 –> Width Equal to Width of HS Input <DHS_MODE> = 0 –> DHS Width is 1 ADCCLK2 Period 7 ADCCLK2 Cycles Latency |
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