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TLV2548MPWREP Datasheet(PDF) 10 Page - Texas Instruments

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Part # TLV2548MPWREP
Description  3.0-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTOPOWER-DOWN
PDF  38 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLV2548MPWREP Datasheet(HTML) 10 Page - Texas Instruments

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SCLK
CS
FS
SDI
INT
EOC
SDO
ID14
OD11
OD10
OD9
ID15
1
2
3
4
7
13
16
1
12
14
15
5
6
ID14
ID13
ID12
ID15
OD4
OD3
OD2
OD1
OD0
SCLK
CS
FS
SDI
INT
EOC
SDO
ID15
ID14
ID13 ID12
OD7
OD5
1
2
3
12
OD11 OD10
OD9
OD6
OD8
ID15
OD10
OD11
ID14
These devices can perform continuous FIFO read cycles (FS = 1) controlled by SCLK; SCLK can stop between each 16 SCLKs.
4
5
6
7
13
14
15
16
1
2
OD0
TLV2548-EP
SLAS668 – OCTOBER 2009
www.ti.com
Figure 3. TLV2548 Read CFR Cycle (FS = 1)
FIFO Read Cycle
The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read
command. The first FIFO content is output immediately before the command is decoded. If this command is not
a FIFO read, then the output is terminated but the first data in the FIFO is retained until a valid FIFO read
command is decoded. Use of more layers of the FIFO reduces the time taken to read multiple data. This is
because the read cycle does not generate EOC or INT, nor does it carry out any conversion.
Figure 4. TLV2548 FIFO Read Cycle (FS = 1)
10
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2548-EP



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