WM9712CLGEFLSLASHV datasheet(51/78 Pages) WOLFSON

51 / 78 page

Production Data

WM9712L

PD, Rev 4.6, November 2011

GPIO AND INTERRUPT CONTROL

The WM9712L has five GPIO pins that operate as defined in the AC’97 Revision 2.2 specification.

Each GPIO pin can be set up as an input or as an output, and has corresponding bits in register 54h

and in slot 12. The state of a GPIO output is determined by sending data through slot 12 of outgoing

frames (SDATAOUT). Data can be returned from a GPIO input by reading the register bit, or

examining slot 12 of incoming frames (SDATAIN). GPIO inputs can be made sticky, and can be

programmed to generate and interrupt, transmitted either through the AC-Link or through a dedicated,

level-mode interrupt pin (GPIO2/IRQ, pin 45).

GPIO pins 2 to 5 are multi-purpose pins that can also be used for other (non-GPIO) purposes, e.g. as

a SPDIF output or to signal pen-down. This is controlled by register 56h.

Independently of the GPIO pins, the WM9712L also has five virtual GPIOs. These are signals from

inside the WM9712L, which are treated as if they were GPIO input signals. From a software

perspective, virtual GPIOs are the same as GPIO pins, but they cannot be set up as outputs, and are

not tied to an actual pin. This allows for simple, uniform processing of different types of signals that

may generate interrupts (e.g. pen down, battery warnings, jack insertion, high-temperature warning,

or GPIO signals).

Figure 15 GPIO Logic

WM9712CLGEFL/V Datasheet(PDF) 51 Page - Wolfson Microelectronics plc