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WM9712CLGEFL/V Datasheet(PDF) 60 Page - Wolfson Microelectronics plc |
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WM9712CLGEFL/V Datasheet(HTML) 60 Page - Wolfson Microelectronics plc |
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60 / 78 page ![]() WM9712L Production Data w PD, Rev 4.6, November 2011 60 SIGNAL RISE AND FALL TIMES BITCLK SYNC SDATAIN SDATAOUT t rise CLK t fall CLK t rise SYNC t fall SYNC t rise DIN t fall DIN t rise DOUT t fall DOUT Figure 19 Signal Rise and Fall Times (50pF External Load) PARAMETER SYMBOL MIN TYP MAX UNIT Incoming signals (from the AC’97 controller to the WM9712L) SDATAOUT rise time triseDOUT 6 ns SDATAOUT fall time tfallDOUT 6 ns SYNC rise time triseSYNC 6 ns SYNC fall time tfallSYNC 6 ns Outgoing signals (from the WM9712L to the AC’97 controller) BITCLK rise time triseCLK 2 6 ns BITCLK fall time tfallCLK 2 6 ns SDATAIN rise time triseDIN 2 6 ns SDATAIN fall time tfallDIN 2 6 ns AC-LINK POWERDOWN SYNC BITCLK SDATAOUT WRITE TO 0X20 DATA PR4 DON'T CARE SDATAIN SLOT 1 SLOT 2 t S2_PDOWN Figure 20 AC-Link Powerdown Timing AC-Link powerdown occurs when PR4 (register 26h, bit 12) is set (see “Power Management” section). PARAMETER SYMBOL MIN TYP MAX UNIT End of Slot 2 to BITCLK and SDATAIN low tS2_PDOWN 1.0 s |
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