WM9712CLGEFLSLASHV datasheet(59/78 Pages) WOLFSON

59 / 78 page

Production Data

WM9712L

PD, Rev 4.6, November 2011

INTERFACE TIMING

Test Characteristics:

DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25C to +85C, unless otherwise stated.

CLOCK SPECIFICATIONS

BITCLK

SYNC

CLK_HIGH

CLK_LOW

CLK_PERIOD

SYNC_HIGH

SYNC_LOW

SYNC_PERIOD

Figure 17 Clock Specifications (50pF External Load)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

BITCLK frequency

12.288

MHz

BITCLK period

tCLK_PERIOD

81.4

BITCLK output jitter

750

BITCLK high pulse width (Note 1)

tCLK_HIGH

40.7

BITCLK low pulse width (Note 1)

tCLK_LOW

40.7

SYNC frequency

kHz

SYNC period

tSYNC_PERIOD

20.8

s

SYNC high pulse width

tSYNC_HIGH

1.3

s

SYNC low pulse width

tSYNC_LOW

19.5

s

Note:

1. Worst case duty cycle restricted to 45/55

DATA SETUP AND HOLD

Figure 18 Data Setup and Hold (50pF External Load)

Note:

Setup and hold times for SDATAIN are with respect to the AC’97 controller, not the WM9712L.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Setup to falling edge of BITCLK

tSETUP

Hold from falling edge of BITCLK

tHOLD

Output valid delay from rising edge of

BITCLK

tCO

WM9712CLGEFL/V Datasheet(PDF) 59 Page - Wolfson Microelectronics plc

WM9712CLGEFL/V Datasheet(HTML) 59 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Download

Link URL