MPXD2005VMM80R datasheet(96/119 Pages) FREESCALE

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PXS20 Microcontroller Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Electrical characteristics

Freescale Semiconductor

3.19.1

Reset sequence duration

Table 29 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in

Section 3.19.2, Reset sequence description.

3.19.2

Reset sequence description

The figures in this section show the internal states of the chip during the five different reset sequences. The doted lines in the

figures indicate the starting point and the end point for which the duration is specified in Table 29. The start point and end point

conditions as well as the reset trigger mapping to the different reset sequences is specified in Section 3.19.3, Reset sequence

trigger mapping.

With the beginning of DRUN mode the first instruction is fetched and executed. At this point application execution starts and

the internal reset sequence is finished.

The figures below show the internal states of the chip during the execution of the reset sequence and the possible states of the

signal pin RESET.

NOTE

RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an

external reset generator or by the chip internal reset circuitry. A high level on this pin can

only be generated by an external pull up resistor which is strong enough to overdrive the

weak internal pull down resistor. The rising edge on RESET in the following figures

indicates the time when the device stops driving it low. The reset sequence durations given

in table Table 29 are applicable only if the internal reset sequence is not prolonged by an

external reset generator keeping RESET asserted low beyond the last PHASE3.

Table 29. RESET sequences

No.

Symbol

Parameter

Conditions

TReset

Unit

Min

Typ

Max1

1 The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET

by an external reset generator.

1TDRB

Destructive Reset Sequence, BIST enabled

cut1

cut2

2TDR

Destructive Reset Sequence, BIST disabled

—

500

4200

5000

s

3TERLB

External Reset Sequence Long, BIST enabled

cut1

cut2

4TFRL

Functional Reset Sequence Long

—

150

400

s

5TFRS

Functional Reset Sequence Short

—

s

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