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MPXD2005VMM80R Datasheet(PDF) 19 Page - Freescale Semiconductor, Inc

Part # MPXD2005VMM80R
Description  PXS20 Microcontroller
PDF  119 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPXD2005VMM80R Datasheet(HTML) 19 Page - Freescale Semiconductor, Inc

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Introduction
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
19
•
Quadrature decode capabilities
•
Counters can share available input pins
•
Count once or repeatedly
•
Preloadable counters
•
Pins available as GPIO when timer functionality not in use
•
DMA support
1.5.32
Sine Wave Generator (SWG)
A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver).
•
Frequency range from 1 kHz to 50 kHz
•
Sine wave amplitude from 0.47 V to 2.26 V
1.5.33
Analog-to-Digital Converter Module (ADC)
The ADC module features include:
Analog part:
•
2 on-chip ADCs
— 12-bit resolution SAR architecture
— A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16 channels)
— One channel dedicated to each T-sensor to enable temperature reading during application
— Separated reference for each ADC
— Shared analog supply voltage for both ADCs
— One sample and hold unit per ADC
— Adjustable sampling and conversion time
Digital part:
•
4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in
the appropriate ADC result location
•
2 modes of operation: Motor Control Mode or Regular Mode
•
Regular mode features
— Register based interface with the CPU: one result register per channel
— ADC state machine managing three request flows: regular command, hardware injected command, software
injected command
— Selectable priority between software and hardware injected commands
— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)
— DMA compatible interface
•
Motor control mode features
— Triggered mode only
— 4 independent result queues (1
 16 entries, 2  8 entries, 1  4 entries)
— Result alignment circuitry (left justified; right justified)
— 32-bit read mode allows to have channel ID on one of the 16-bit parts
— DMA compatible interfaces
•
Built-in self-test features triggered by software



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