PIC24F32KA302-ISLASHML datasheet(134/364 Pages) MICROCHIP

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PIC24FV32KA304 FAMILY

DS39995D-page 134

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10.5

Doze Mode

Generally, changing clock speed and invoking one of

the power-saving modes are the preferred strategies

for reducing power consumption. There may be circum-

stances, however, where this is not practical. For

example, it may be necessary for an application to

maintain uninterrupted synchronous communication,

even while it is doing nothing else. Reducing system

clock speed may introduce communication errors,

while using a power-saving mode may stop

communications completely.

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock

continues to operate from the same source and at the

same speed. Peripheral modules continue to be

clocked at the same speed, while the CPU clock speed

is reduced. Synchronization between the two clock

domains is maintained, allowing the peripherals to

access the SFRs while the CPU executes code at a

slower rate.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>).

There

are

eight

possible

configurations, from 1:1 to 1:128, with 1:1 being the

default.

It is also possible to use Doze mode to selectively reduce

power consumption in event driven applications. This

allows clock-sensitive functions, such as synchronous

communications, to continue without interruption. Mean-

while, the CPU Idles, waiting for something to invoke an

interrupt routine. Enabling the automatic return to

full-speed CPU operation on interrupts is enabled by

setting the ROI bit (CLKDIV<15>). By default, interrupt

events have no effect on Doze mode operation.

10.6

Selective Peripheral Module

Control

Idle and Doze modes allow users to substantially

reduce power consumption by slowing or stopping the

CPU clock. Even so, peripheral modules still remain

clocked, and thus, consume power. There may be

cases where the application needs what these modes

do not provide: the allocation of power resources to

CPU processing, with minimal power consumption

from the peripherals.

PIC24F devices address this requirement by allowing

peripheral modules to be selectively disabled, reducing

or eliminating their power consumption. This can be

done with two control bits:

• The Peripheral Enable bit, generically named,

“XXXEN”, located in the module’s main control

SFR.

• The Peripheral Module Disable (PMD) bit,

generically named, “XXXMD”, located in one of

the PMD Control registers.

Both bits have similar functions in enabling or disabling its

associated module. Setting the PMDx bits for a module

disables all clock sources to that module, reducing its

power consumption to an absolute minimum. In this

state, the control and status registers associated with the

peripheral will also be disabled, so writes to those

registers will have no effect, and read values will be

invalid. Many peripheral modules have a corresponding

PMDx bit.

In contrast, disabling a module by clearing its XXXEN

bit, disables its functionality, but leaves its registers

available to be read and written to. Power consumption

is reduced, but not by as much as the PMDx bits are

used. Most peripheral modules have an enable bit;

exceptions include capture, compare and RTCC.

To achieve more selective power savings, peripheral

modules can also be selectively disabled when the

device enters Idle mode. This is done through the control

bit of the generic name format, “XXXIDL”. By default, all

modules that can operate during Idle mode will do so.

Using the disable on Idle feature disables the module

while in Idle mode, allowing further reduction of power

consumption during Idle mode, enhancing power

savings for extremely critical power applications.

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